1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 46 47import scala.math.min 48 49case object XSTileKey extends Field[Seq[XSCoreParameters]] 50 51case object XSCoreParamsKey extends Field[XSCoreParameters] 52 53case class XSCoreParameters 54( 55 HasPrefetch: Boolean = false, 56 HartId: Int = 0, 57 XLEN: Int = 64, 58 VLEN: Int = 128, 59 ELEN: Int = 64, 60 HasMExtension: Boolean = true, 61 HasCExtension: Boolean = true, 62 HasDiv: Boolean = true, 63 HasICache: Boolean = true, 64 HasDCache: Boolean = true, 65 AddrBits: Int = 64, 66 VAddrBits: Int = 39, 67 HasFPU: Boolean = true, 68 HasVPU: Boolean = true, 69 HasCustomCSRCacheOp: Boolean = true, 70 FetchWidth: Int = 8, 71 AsidLength: Int = 16, 72 EnableBPU: Boolean = true, 73 EnableBPD: Boolean = true, 74 EnableRAS: Boolean = true, 75 EnableLB: Boolean = false, 76 EnableLoop: Boolean = true, 77 EnableSC: Boolean = true, 78 EnbaleTlbDebug: Boolean = false, 79 EnableJal: Boolean = false, 80 EnableFauFTB: Boolean = true, 81 UbtbGHRLength: Int = 4, 82 // HistoryLength: Int = 512, 83 EnableGHistDiff: Boolean = true, 84 EnableCommitGHistDiff: Boolean = true, 85 UbtbSize: Int = 256, 86 FtbSize: Int = 2048, 87 RasSize: Int = 32, 88 CacheLineSize: Int = 512, 89 FtbWays: Int = 4, 90 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 // Seq(( 2048, 2, 8), 93 // ( 2048, 9, 8), 94 // ( 2048, 13, 8), 95 // ( 2048, 20, 8), 96 // ( 2048, 26, 8), 97 // ( 2048, 44, 8), 98 // ( 2048, 73, 8), 99 // ( 2048, 256, 8)), 100 Seq(( 4096, 8, 8), 101 ( 4096, 13, 8), 102 ( 4096, 32, 8), 103 ( 4096, 119, 8)), 104 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 256, 4, 9), 107 ( 256, 8, 9), 108 ( 512, 13, 9), 109 ( 512, 16, 9), 110 ( 512, 32, 9)), 111 SCNRows: Int = 512, 112 SCNTables: Int = 4, 113 SCCtrBits: Int = 6, 114 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 115 numBr: Int = 2, 116 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 117 ((resp_in: BranchPredictionResp, p: Parameters) => { 118 val ftb = Module(new FTB()(p)) 119 val ubtb =Module(new FauFTB()(p)) 120 // val bim = Module(new BIM()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(ubtb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 // ubtb.io.resp_in(0) := resp_in 128 // bim.io.resp_in(0) := ubtb.io.resp 129 // btb.io.resp_in(0) := bim.io.resp 130 // tage.io.resp_in(0) := btb.io.resp 131 // loop.io.resp_in(0) := tage.io.resp 132 ubtb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := ubtb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }), 140 IBufSize: Int = 48, 141 DecodeWidth: Int = 6, 142 RenameWidth: Int = 6, 143 CommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 FtqSize: Int = 64, 146 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 147 IntLogicRegs: Int = 32, 148 FpLogicRegs: Int = 33, 149 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 150 VCONFIG_IDX: Int = 32, 151 NRPhyRegs: Int = 192, 152 IntPhyRegs: Int = 192, 153 VfPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 80, 155 LoadQueueRARSize: Int = 80, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 80, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 256, 166 RabSize: Int = 256, 167 dpParams: DispatchParameters = DispatchParameters( 168 IntDqSize = 16, 169 FpDqSize = 16, 170 LsDqSize = 16, 171 IntDqDeqWidth = 6, 172 FpDqDeqWidth = 6, 173 LsDqDeqWidth = 6, 174 ), 175 intPreg: PregParams = IntPregParams( 176 numEntries = 256, 177 numRead = 14, 178 numWrite = 8, 179 ), 180 vfPreg: VfPregParams = VfPregParams( 181 numEntries = 256, 182 numRead = 14, 183 numWrite = 8, 184 ), 185 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 186 LoadPipelineWidth: Int = 2, 187 StorePipelineWidth: Int = 2, 188 VecMemSrcInWidth: Int = 2, 189 VecMemInstWbWidth: Int = 1, 190 VecMemDispatchWidth: Int = 1, 191 StoreBufferSize: Int = 16, 192 StoreBufferThreshold: Int = 7, 193 EnsbufferWidth: Int = 2, 194 UncacheBufferSize: Int = 4, 195 EnableLoadToLoadForward: Boolean = true, 196 EnableFastForward: Boolean = false, 197 EnableLdVioCheckAfterReset: Boolean = true, 198 EnableSoftPrefetchAfterReset: Boolean = true, 199 EnableCacheErrorAfterReset: Boolean = true, 200 EnableDCacheWPU: Boolean = false, 201 EnableAccurateLoadError: Boolean = true, 202 EnableUncacheWriteOutstanding: Boolean = false, 203 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 204 ReSelectLen: Int = 7, // load replay queue replay select counter len 205 itlbParameters: TLBParameters = TLBParameters( 206 name = "itlb", 207 fetchi = true, 208 useDmode = false, 209 normalNWays = 32, 210 normalReplacer = Some("plru"), 211 superNWays = 4, 212 superReplacer = Some("plru") 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 sttlbParameters: TLBParameters = TLBParameters( 230 name = "sttlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 pftlbParameters: TLBParameters = TLBParameters( 243 name = "pftlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 refillBothTlb: Boolean = false, 256 btlbParameters: TLBParameters = TLBParameters( 257 name = "btlb", 258 normalNSets = 1, 259 normalNWays = 64, 260 superNWays = 4, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 64, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 def intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 val pregBits = intPreg.addrWidth 302 val numRfRead = intPreg.numRead 303 val numRfWrite = intPreg.numWrite 304 SchdBlockParams(Seq( 305 IssueBlockParams(Seq( 306 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 307 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 308 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 311 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 312 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 315 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams(Seq(I2fCfg, VSetRiWiCfg, VSetRiWvfCfg), Seq(VecWB(port = 6, Int.MaxValue), IntWB(port = 7, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 319 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 320 ), 321 numPregs = intPreg.numEntries, 322 numRfReadWrite = Some((numRfRead, numRfWrite)), 323 numDeqOutside = 0, 324 schdType = schdType, 325 rfDataWidth = intPreg.dataCfg.dataWidth, 326 numUopIn = dpParams.IntDqDeqWidth, 327 ) 328 } 329 def vfSchdParams = { 330 implicit val schdType: SchedulerType = VfScheduler() 331 val pregBits = vfPreg.addrWidth 332 val numRfRead = vfPreg.numRead 333 val numRfWrite = vfPreg.numWrite 334 SchdBlockParams(Seq( 335 IssueBlockParams(Seq( 336 ExeUnitParams(Seq(VialuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 337 ExeUnitParams(Seq(VimacCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 338 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 339 IssueBlockParams(Seq( 340 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 341 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 342 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 343 ), 344 numPregs = vfPreg.numEntries, 345 numRfReadWrite = Some((numRfRead, numRfWrite)), 346 numDeqOutside = 0, 347 schdType = schdType, 348 rfDataWidth = vfPreg.dataCfg.dataWidth, 349 numUopIn = dpParams.FpDqDeqWidth, 350 ) 351 } 352 def memSchdParams = { 353 implicit val schdType: SchedulerType = MemScheduler() 354 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 355 val rfDataWidth = 64 356 357 SchdBlockParams(Seq( 358 IssueBlockParams(Seq( 359 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VfWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 360 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VfWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 361 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 362 IssueBlockParams(Seq( 363 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 364 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 365 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 366 IssueBlockParams(Seq( 367 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 368 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 369 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 370 IssueBlockParams(Seq( 371 ExeUnitParams(Seq(VlduCfg), Seq(VecWB(6, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 372 ExeUnitParams(Seq(VlduCfg), Seq(VecWB(7, 0)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 373 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 374 ), 375 numPregs = intPreg.numEntries max vfPreg.numEntries, 376 numRfReadWrite = None, 377 numDeqOutside = 0, 378 schdType = schdType, 379 rfDataWidth = rfDataWidth, 380 numUopIn = dpParams.LsDqDeqWidth, 381 ) 382 } 383 384 def backendParams: BackendParams = backend.BackendParams(Map( 385 IntScheduler() -> intSchdParams, 386 VfScheduler() -> vfSchdParams, 387 MemScheduler() -> memSchdParams, 388 ), Seq( 389 intPreg, 390 vfPreg, 391 )) 392} 393 394case object DebugOptionsKey extends Field[DebugOptions] 395 396case class DebugOptions 397( 398 FPGAPlatform: Boolean = false, 399 EnableDifftest: Boolean = false, 400 AlwaysBasicDiff: Boolean = true, 401 EnableDebug: Boolean = false, 402 EnablePerfDebug: Boolean = true, 403 UseDRAMSim: Boolean = false, 404 EnableConstantin: Boolean = false, 405 EnableTopDown: Boolean = false 406) 407 408trait HasXSParameter { 409 410 implicit val p: Parameters 411 412 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 413 414 val coreParams = p(XSCoreParamsKey) 415 val env = p(DebugOptionsKey) 416 417 val XLEN = coreParams.XLEN 418 val VLEN = coreParams.VLEN 419 val ELEN = coreParams.ELEN 420 val minFLen = 32 421 val fLen = 64 422 def xLen = XLEN 423 424 val HasMExtension = coreParams.HasMExtension 425 val HasCExtension = coreParams.HasCExtension 426 val HasDiv = coreParams.HasDiv 427 val HasIcache = coreParams.HasICache 428 val HasDcache = coreParams.HasDCache 429 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 430 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 431 val AsidLength = coreParams.AsidLength 432 val ReSelectLen = coreParams.ReSelectLen 433 val AddrBytes = AddrBits / 8 // unused 434 val DataBits = XLEN 435 val DataBytes = DataBits / 8 436 val HasFPU = coreParams.HasFPU 437 val HasVPU = coreParams.HasVPU 438 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 439 val FetchWidth = coreParams.FetchWidth 440 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 441 val EnableBPU = coreParams.EnableBPU 442 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 443 val EnableRAS = coreParams.EnableRAS 444 val EnableLB = coreParams.EnableLB 445 val EnableLoop = coreParams.EnableLoop 446 val EnableSC = coreParams.EnableSC 447 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 448 val HistoryLength = coreParams.HistoryLength 449 val EnableGHistDiff = coreParams.EnableGHistDiff 450 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 451 val UbtbGHRLength = coreParams.UbtbGHRLength 452 val UbtbSize = coreParams.UbtbSize 453 val EnableFauFTB = coreParams.EnableFauFTB 454 val FtbSize = coreParams.FtbSize 455 val FtbWays = coreParams.FtbWays 456 val RasSize = coreParams.RasSize 457 458 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 459 coreParams.branchPredictor(resp_in, p) 460 } 461 val numBr = coreParams.numBr 462 val TageTableInfos = coreParams.TageTableInfos 463 val TageBanks = coreParams.numBr 464 val SCNRows = coreParams.SCNRows 465 val SCCtrBits = coreParams.SCCtrBits 466 val SCHistLens = coreParams.SCHistLens 467 val SCNTables = coreParams.SCNTables 468 469 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 470 case ((n, cb), h) => (n, cb, h) 471 } 472 val ITTageTableInfos = coreParams.ITTageTableInfos 473 type FoldedHistoryInfo = Tuple2[Int, Int] 474 val foldedGHistInfos = 475 (TageTableInfos.map{ case (nRows, h, t) => 476 if (h > 0) 477 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 478 else 479 Set[FoldedHistoryInfo]() 480 }.reduce(_++_).toSet ++ 481 SCTableInfos.map{ case (nRows, _, h) => 482 if (h > 0) 483 Set((h, min(log2Ceil(nRows/TageBanks), h))) 484 else 485 Set[FoldedHistoryInfo]() 486 }.reduce(_++_).toSet ++ 487 ITTageTableInfos.map{ case (nRows, h, t) => 488 if (h > 0) 489 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 490 else 491 Set[FoldedHistoryInfo]() 492 }.reduce(_++_) ++ 493 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 494 ).toList 495 496 497 498 val CacheLineSize = coreParams.CacheLineSize 499 val CacheLineHalfWord = CacheLineSize / 16 500 val ExtHistoryLength = HistoryLength + 64 501 val IBufSize = coreParams.IBufSize 502 val DecodeWidth = coreParams.DecodeWidth 503 val RenameWidth = coreParams.RenameWidth 504 val CommitWidth = coreParams.CommitWidth 505 val MaxUopSize = coreParams.MaxUopSize 506 val FtqSize = coreParams.FtqSize 507 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 508 val IntLogicRegs = coreParams.IntLogicRegs 509 val FpLogicRegs = coreParams.FpLogicRegs 510 val VecLogicRegs = coreParams.VecLogicRegs 511 val VCONFIG_IDX = coreParams.VCONFIG_IDX 512 val NRPhyRegs = coreParams.NRPhyRegs 513 val PhyRegIdxWidth = log2Up(NRPhyRegs) 514 val IntPhyRegs = coreParams.IntPhyRegs 515 val VfPhyRegs = coreParams.VfPhyRegs 516 val IntPregIdxWidth = log2Up(IntPhyRegs) 517 val VfPregIdxWidth = log2Up(VfPhyRegs) 518 val RobSize = coreParams.RobSize 519 val RabSize = coreParams.RabSize 520 val IntRefCounterWidth = log2Ceil(RobSize) 521 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 522 val LoadQueueRARSize = coreParams.LoadQueueRARSize 523 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 524 val RollbackGroupSize = coreParams.RollbackGroupSize 525 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 526 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 527 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 528 val StoreQueueSize = coreParams.StoreQueueSize 529 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 530 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 531 val VlsQueueSize = coreParams.VlsQueueSize 532 val dpParams = coreParams.dpParams 533 534 def backendParams: BackendParams = coreParams.backendParams 535 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 536 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 537 val LoadPipelineWidth = coreParams.LoadPipelineWidth 538 val StorePipelineWidth = coreParams.StorePipelineWidth 539 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 540 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 541 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 542 val StoreBufferSize = coreParams.StoreBufferSize 543 val StoreBufferThreshold = coreParams.StoreBufferThreshold 544 val EnsbufferWidth = coreParams.EnsbufferWidth 545 val UncacheBufferSize = coreParams.UncacheBufferSize 546 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 547 val EnableFastForward = coreParams.EnableFastForward 548 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 549 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 550 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 551 val EnableDCacheWPU = coreParams.EnableDCacheWPU 552 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 553 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 554 val asidLen = coreParams.MMUAsidLen 555 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 556 val refillBothTlb = coreParams.refillBothTlb 557 val itlbParams = coreParams.itlbParameters 558 val ldtlbParams = coreParams.ldtlbParameters 559 val sttlbParams = coreParams.sttlbParameters 560 val pftlbParams = coreParams.pftlbParameters 561 val btlbParams = coreParams.btlbParameters 562 val l2tlbParams = coreParams.l2tlbParameters 563 val NumPerfCounters = coreParams.NumPerfCounters 564 565 val instBytes = if (HasCExtension) 2 else 4 566 val instOffsetBits = log2Ceil(instBytes) 567 568 val icacheParameters = coreParams.icacheParameters 569 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 570 571 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 572 // for constrained LR/SC loop 573 val LRSCCycles = 64 574 // for lr storm 575 val LRSCBackOff = 8 576 577 // cache hierarchy configurations 578 val l1BusDataWidth = 256 579 580 // load violation predict 581 val ResetTimeMax2Pow = 20 //1078576 582 val ResetTimeMin2Pow = 10 //1024 583 // wait table parameters 584 val WaitTableSize = 1024 585 val MemPredPCWidth = log2Up(WaitTableSize) 586 val LWTUse2BitCounter = true 587 // store set parameters 588 val SSITSize = WaitTableSize 589 val LFSTSize = 32 590 val SSIDWidth = log2Up(LFSTSize) 591 val LFSTWidth = 4 592 val StoreSetEnable = true // LWT will be disabled if SS is enabled 593 val LFSTEnable = false 594 595 val PCntIncrStep: Int = 6 596 val numPCntHc: Int = 25 597 val numPCntPtw: Int = 19 598 599 val numCSRPCntFrontend = 8 600 val numCSRPCntCtrl = 8 601 val numCSRPCntLsu = 8 602 val numCSRPCntHc = 5 603} 604