xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 870f462d572cd0ef6bf86c91dcda5a5fab6e99d3) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import huancun._
23import system.SoCParamsKey
24import xiangshan.backend.datapath.RdConfig._
25import xiangshan.backend.datapath.WbConfig._
26import xiangshan.backend.dispatch.DispatchParameters
27import xiangshan.backend.exu.ExeUnitParams
28import xiangshan.backend.fu.FuConfig._
29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler}
30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams}
31import xiangshan.backend.BackendParams
32import xiangshan.cache.DCacheParameters
33import xiangshan.cache.prefetch._
34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB}
35import xiangshan.frontend.icache.ICacheParameters
36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
37import xiangshan.frontend._
38import xiangshan.frontend.icache.ICacheParameters
39
40import freechips.rocketchip.diplomacy.AddressSet
41import system.SoCParamsKey
42import huancun._
43import huancun.debug._
44import xiangshan.cache.wpu.WPUParameters
45import coupledL2._
46import xiangshan.backend.datapath.WakeUpConfig
47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams}
48
49import scala.math.min
50
51case object XSTileKey extends Field[Seq[XSCoreParameters]]
52
53case object XSCoreParamsKey extends Field[XSCoreParameters]
54
55case class XSCoreParameters
56(
57  HasPrefetch: Boolean = false,
58  HartId: Int = 0,
59  XLEN: Int = 64,
60  VLEN: Int = 128,
61  ELEN: Int = 64,
62  HasMExtension: Boolean = true,
63  HasCExtension: Boolean = true,
64  HasDiv: Boolean = true,
65  HasICache: Boolean = true,
66  HasDCache: Boolean = true,
67  AddrBits: Int = 64,
68  VAddrBits: Int = 39,
69  HasFPU: Boolean = true,
70  HasVPU: Boolean = true,
71  HasCustomCSRCacheOp: Boolean = true,
72  FetchWidth: Int = 8,
73  AsidLength: Int = 16,
74  EnableBPU: Boolean = true,
75  EnableBPD: Boolean = true,
76  EnableRAS: Boolean = true,
77  EnableLB: Boolean = false,
78  EnableLoop: Boolean = true,
79  EnableSC: Boolean = true,
80  EnbaleTlbDebug: Boolean = false,
81  EnableJal: Boolean = false,
82  EnableFauFTB: Boolean = true,
83  UbtbGHRLength: Int = 4,
84  // HistoryLength: Int = 512,
85  EnableGHistDiff: Boolean = true,
86  EnableCommitGHistDiff: Boolean = true,
87  UbtbSize: Int = 256,
88  FtbSize: Int = 2048,
89  RasSize: Int = 32,
90  CacheLineSize: Int = 512,
91  FtbWays: Int = 4,
92  TageTableInfos: Seq[Tuple3[Int,Int,Int]] =
93  //       Sets  Hist   Tag
94    // Seq(( 2048,    2,    8),
95    //     ( 2048,    9,    8),
96    //     ( 2048,   13,    8),
97    //     ( 2048,   20,    8),
98    //     ( 2048,   26,    8),
99    //     ( 2048,   44,    8),
100    //     ( 2048,   73,    8),
101    //     ( 2048,  256,    8)),
102    Seq(( 4096,    8,    8),
103        ( 4096,   13,    8),
104        ( 4096,   32,    8),
105        ( 4096,  119,    8)),
106  ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] =
107  //      Sets  Hist   Tag
108    Seq(( 256,    4,    9),
109        ( 256,    8,    9),
110        ( 512,   13,    9),
111        ( 512,   16,    9),
112        ( 512,   32,    9)),
113  SCNRows: Int = 512,
114  SCNTables: Int = 4,
115  SCCtrBits: Int = 6,
116  SCHistLens: Seq[Int] = Seq(0, 4, 10, 16),
117  numBr: Int = 2,
118  branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
119    ((resp_in: BranchPredictionResp, p: Parameters) => {
120      val ftb = Module(new FTB()(p))
121      val ubtb =Module(new FauFTB()(p))
122      // val bim = Module(new BIM()(p))
123      val tage = Module(new Tage_SC()(p))
124      val ras = Module(new RAS()(p))
125      val ittage = Module(new ITTage()(p))
126      val preds = Seq(ubtb, tage, ftb, ittage, ras)
127      preds.map(_.io := DontCare)
128
129      // ubtb.io.resp_in(0)  := resp_in
130      // bim.io.resp_in(0)   := ubtb.io.resp
131      // btb.io.resp_in(0)   := bim.io.resp
132      // tage.io.resp_in(0)  := btb.io.resp
133      // loop.io.resp_in(0)  := tage.io.resp
134      ubtb.io.in.bits.resp_in(0) := resp_in
135      tage.io.in.bits.resp_in(0) := ubtb.io.out
136      ftb.io.in.bits.resp_in(0)  := tage.io.out
137      ittage.io.in.bits.resp_in(0)  := ftb.io.out
138      ras.io.in.bits.resp_in(0) := ittage.io.out
139
140      (preds, ras.io.out)
141    }),
142  IBufSize: Int = 48,
143  DecodeWidth: Int = 6,
144  RenameWidth: Int = 6,
145  CommitWidth: Int = 6,
146  MaxUopSize: Int = 65,
147  EnableRenameSnapshot: Boolean = true,
148  RenameSnapshotNum: Int = 4,
149  FtqSize: Int = 64,
150  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
151  IntLogicRegs: Int = 32,
152  FpLogicRegs: Int = 33,
153  VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig
154  VCONFIG_IDX: Int = 32,
155  NRPhyRegs: Int = 192,
156  VirtualLoadQueueSize: Int = 80,
157  LoadQueueRARSize: Int = 80,
158  LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2.
159  RollbackGroupSize: Int = 8,
160  LoadQueueReplaySize: Int = 72,
161  LoadUncacheBufferSize: Int = 20,
162  LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks
163  StoreQueueSize: Int = 64,
164  StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
165  StoreQueueForwardWithMask: Boolean = true,
166  VlsQueueSize: Int = 8,
167  RobSize: Int = 256,
168  RabSize: Int = 256,
169  dpParams: DispatchParameters = DispatchParameters(
170    IntDqSize = 16,
171    FpDqSize = 16,
172    LsDqSize = 16,
173    IntDqDeqWidth = 6,
174    FpDqDeqWidth = 6,
175    LsDqDeqWidth = 6,
176  ),
177  intPreg: PregParams = IntPregParams(
178    numEntries = 192,
179    numRead = None,
180    numWrite = None,
181  ),
182  vfPreg: VfPregParams = VfPregParams(
183    numEntries = 192,
184    numRead = None,
185    numWrite = None,
186  ),
187  prefetcher: Option[PrefetcherParams] = Some(SMSParams()),
188  LoadPipelineWidth: Int = 2,
189  StorePipelineWidth: Int = 2,
190  VecMemSrcInWidth: Int = 2,
191  VecMemInstWbWidth: Int = 1,
192  VecMemDispatchWidth: Int = 1,
193  StoreBufferSize: Int = 16,
194  StoreBufferThreshold: Int = 7,
195  EnsbufferWidth: Int = 2,
196  UncacheBufferSize: Int = 4,
197  EnableLoadToLoadForward: Boolean = true,
198  EnableFastForward: Boolean = true,
199  EnableLdVioCheckAfterReset: Boolean = true,
200  EnableSoftPrefetchAfterReset: Boolean = true,
201  EnableCacheErrorAfterReset: Boolean = true,
202  EnableAccurateLoadError: Boolean = true,
203  EnableUncacheWriteOutstanding: Boolean = false,
204  MMUAsidLen: Int = 16, // max is 16, 0 is not supported now
205  ReSelectLen: Int = 7, // load replay queue replay select counter len
206  iwpuParameters: WPUParameters = WPUParameters(
207    enWPU = false,
208    algoName = "mmru",
209    isICache = true,
210  ),
211  dwpuParameters: WPUParameters = WPUParameters(
212    enWPU = false,
213    algoName = "mmru",
214    enCfPred = false,
215    isICache = false,
216  ),
217  itlbParameters: TLBParameters = TLBParameters(
218    name = "itlb",
219    fetchi = true,
220    useDmode = false,
221    normalNWays = 32,
222    normalReplacer = Some("plru"),
223    superNWays = 4,
224    superReplacer = Some("plru")
225  ),
226  itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1,
227  ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1,
228  ldtlbParameters: TLBParameters = TLBParameters(
229    name = "ldtlb",
230    normalNSets = 64,
231    normalNWays = 1,
232    normalAssociative = "sa",
233    normalReplacer = Some("setplru"),
234    superNWays = 16,
235    normalAsVictim = true,
236    outReplace = false,
237    partialStaticPMP = true,
238    outsideRecvFlush = true,
239    saveLevel = true
240  ),
241  sttlbParameters: TLBParameters = TLBParameters(
242    name = "sttlb",
243    normalNSets = 64,
244    normalNWays = 1,
245    normalAssociative = "sa",
246    normalReplacer = Some("setplru"),
247    superNWays = 16,
248    normalAsVictim = true,
249    outReplace = false,
250    partialStaticPMP = true,
251    outsideRecvFlush = true,
252    saveLevel = true
253  ),
254  pftlbParameters: TLBParameters = TLBParameters(
255    name = "pftlb",
256    normalNSets = 64,
257    normalNWays = 1,
258    normalAssociative = "sa",
259    normalReplacer = Some("setplru"),
260    superNWays = 16,
261    normalAsVictim = true,
262    outReplace = false,
263    partialStaticPMP = true,
264    outsideRecvFlush = true,
265    saveLevel = true
266  ),
267  refillBothTlb: Boolean = false,
268  btlbParameters: TLBParameters = TLBParameters(
269    name = "btlb",
270    normalNSets = 1,
271    normalNWays = 64,
272    superNWays = 4,
273  ),
274  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
275  NumPerfCounters: Int = 16,
276  icacheParameters: ICacheParameters = ICacheParameters(
277    tagECC = Some("parity"),
278    dataECC = Some("parity"),
279    replacer = Some("setplru"),
280    nMissEntries = 2,
281    nProbeEntries = 2,
282    nPrefetchEntries = 12,
283    nPrefBufferEntries = 64,
284    hasPrefetch = true,
285  ),
286  dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
287    tagECC = Some("secded"),
288    dataECC = Some("secded"),
289    replacer = Some("setplru"),
290    nMissEntries = 16,
291    nProbeEntries = 8,
292    nReleaseEntries = 18
293  )),
294  L2CacheParamsOpt: Option[L2Param] = Some(L2Param(
295    name = "l2",
296    ways = 8,
297    sets = 1024, // default 512KB L2
298    prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams())
299  )),
300  L2NBanks: Int = 1,
301  usePTWRepeater: Boolean = false,
302  softTLB: Boolean = false, // dpi-c l1tlb debug only
303  softPTW: Boolean = false, // dpi-c l2tlb debug only
304  softPTWDelay: Int = 1
305){
306  def vlWidth = log2Up(VLEN) + 1
307
308  val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
309  val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
310
311  val intSchdParams = {
312    implicit val schdType: SchedulerType = IntScheduler()
313    SchdBlockParams(Seq(
314      IssueBlockParams(Seq(
315        ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))),
316        ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))),
317      ), numEntries = 8, numEnq = 2),
318      IssueBlockParams(Seq(
319        ExeUnitParams("IEX2", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))),
320        ExeUnitParams("IEX3", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))),
321      ), numEntries = 8, numEnq = 2),
322      IssueBlockParams(Seq(
323        ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))),
324        ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))),
325      ), numEntries = 8, numEnq = 2),
326      IssueBlockParams(Seq(
327        ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))),
328      ), numEntries = 8, numEnq = 2),
329      IssueBlockParams(Seq(
330        ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))),
331      ), numEntries = 8, numEnq = 2),
332    ),
333      numPregs = intPreg.numEntries,
334      numDeqOutside = 0,
335      schdType = schdType,
336      rfDataWidth = intPreg.dataCfg.dataWidth,
337      numUopIn = dpParams.IntDqDeqWidth,
338    )
339  }
340  val vfSchdParams = {
341    implicit val schdType: SchedulerType = VfScheduler()
342    SchdBlockParams(Seq(
343      IssueBlockParams(Seq(
344        ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))),
345        ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))),
346      ), numEntries = 8, numEnq = 2),
347      IssueBlockParams(Seq(
348        ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))),
349        ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 3, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))),
350      ), numEntries = 8, numEnq = 2),
351      IssueBlockParams(Seq(
352        ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))),
353        ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))),
354      ), numEntries = 8, numEnq = 2),
355      IssueBlockParams(Seq(
356        ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))),
357      ), numEntries = 8, numEnq = 2),
358    ),
359      numPregs = vfPreg.numEntries,
360      numDeqOutside = 0,
361      schdType = schdType,
362      rfDataWidth = vfPreg.dataCfg.dataWidth,
363      numUopIn = dpParams.FpDqDeqWidth,
364    )
365  }
366
367  val memSchdParams = {
368    implicit val schdType: SchedulerType = MemScheduler()
369    val rfDataWidth = 64
370
371    SchdBlockParams(Seq(
372      IssueBlockParams(Seq(
373        ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))),
374        ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))),
375      ), numEntries = 8, numEnq = 2),
376      IssueBlockParams(Seq(
377        ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))),
378        ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))),
379      ), numEntries = 8, numEnq = 2),
380      IssueBlockParams(Seq(
381        ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))),
382        ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))),
383      ), numEntries = 8, numEnq = 2),
384      IssueBlockParams(Seq(
385        ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))),
386        ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))),
387      ), numEntries = 8, numEnq = 2),
388    ),
389      numPregs = intPreg.numEntries max vfPreg.numEntries,
390      numDeqOutside = 0,
391      schdType = schdType,
392      rfDataWidth = rfDataWidth,
393      numUopIn = dpParams.LsDqDeqWidth,
394    )
395  }
396
397  def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth
398
399  def iqWakeUpParams = {
400    Seq(
401      WakeUpConfig("IEX0" -> "IEX0"),
402      WakeUpConfig("IEX0" -> "IEX1"),
403      WakeUpConfig("IEX1" -> "IEX0"),
404      WakeUpConfig("IEX1" -> "IEX1"),
405      WakeUpConfig("IEX0" -> "BJU0"),
406      WakeUpConfig("IEX0" -> "BJU1"),
407      WakeUpConfig("IEX1" -> "BJU0"),
408      WakeUpConfig("IEX1" -> "BJU1"),
409      WakeUpConfig("IEX0" -> "LDU0"),
410      WakeUpConfig("IEX0" -> "LDU1"),
411      WakeUpConfig("IEX1" -> "LDU0"),
412      WakeUpConfig("IEX1" -> "LDU1"),
413      WakeUpConfig("IEX0" -> "STA0"),
414      WakeUpConfig("IEX0" -> "STA1"),
415      WakeUpConfig("IEX1" -> "STA0"),
416      WakeUpConfig("IEX1" -> "STA1"),
417      WakeUpConfig("IMISC0" -> "FEX0"),
418      WakeUpConfig("IMISC0" -> "FEX1"),
419      WakeUpConfig("IMISC0" -> "FEX2"),
420      WakeUpConfig("IMISC0" -> "FEX3"),
421      WakeUpConfig("IMISC0" -> "FEX4"),
422      WakeUpConfig("FEX3" -> "FEX0"),
423      WakeUpConfig("FEX3" -> "FEX1"),
424      WakeUpConfig("FEX3" -> "FEX2"),
425      WakeUpConfig("FEX3" -> "FEX3"),
426    )
427  }
428
429  def backendParams: BackendParams = backend.BackendParams(
430    Map(
431      IntScheduler() -> intSchdParams,
432      VfScheduler() -> vfSchdParams,
433      MemScheduler() -> memSchdParams,
434    ),
435    Seq(
436      intPreg,
437      vfPreg,
438    ),
439    iqWakeUpParams,
440  )
441}
442
443case object DebugOptionsKey extends Field[DebugOptions]
444
445case class DebugOptions
446(
447  FPGAPlatform: Boolean = false,
448  EnableDifftest: Boolean = false,
449  AlwaysBasicDiff: Boolean = true,
450  EnableDebug: Boolean = false,
451  EnablePerfDebug: Boolean = true,
452  UseDRAMSim: Boolean = false,
453  EnableConstantin: Boolean = false,
454  EnableChiselDB: Boolean = false,
455  AlwaysBasicDB: Boolean = true,
456)
457
458trait HasXSParameter {
459
460  implicit val p: Parameters
461
462  val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits
463
464  val coreParams = p(XSCoreParamsKey)
465  val env = p(DebugOptionsKey)
466
467  val XLEN = coreParams.XLEN
468  val VLEN = coreParams.VLEN
469  val ELEN = coreParams.ELEN
470  val minFLen = 32
471  val fLen = 64
472  def xLen = XLEN
473
474  val HasMExtension = coreParams.HasMExtension
475  val HasCExtension = coreParams.HasCExtension
476  val HasDiv = coreParams.HasDiv
477  val HasIcache = coreParams.HasICache
478  val HasDcache = coreParams.HasDCache
479  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
480  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
481  val AsidLength = coreParams.AsidLength
482  val ReSelectLen = coreParams.ReSelectLen
483  val AddrBytes = AddrBits / 8 // unused
484  val DataBits = XLEN
485  val DataBytes = DataBits / 8
486  val VDataBytes = VLEN / 8
487  val HasFPU = coreParams.HasFPU
488  val HasVPU = coreParams.HasVPU
489  val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp
490  val FetchWidth = coreParams.FetchWidth
491  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
492  val EnableBPU = coreParams.EnableBPU
493  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
494  val EnableRAS = coreParams.EnableRAS
495  val EnableLB = coreParams.EnableLB
496  val EnableLoop = coreParams.EnableLoop
497  val EnableSC = coreParams.EnableSC
498  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
499  val HistoryLength = coreParams.HistoryLength
500  val EnableGHistDiff = coreParams.EnableGHistDiff
501  val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff
502  val UbtbGHRLength = coreParams.UbtbGHRLength
503  val UbtbSize = coreParams.UbtbSize
504  val EnableFauFTB = coreParams.EnableFauFTB
505  val FtbSize = coreParams.FtbSize
506  val FtbWays = coreParams.FtbWays
507  val RasSize = coreParams.RasSize
508
509  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = {
510    coreParams.branchPredictor(resp_in, p)
511  }
512  val numBr = coreParams.numBr
513  val TageTableInfos = coreParams.TageTableInfos
514  val TageBanks = coreParams.numBr
515  val SCNRows = coreParams.SCNRows
516  val SCCtrBits = coreParams.SCCtrBits
517  val SCHistLens = coreParams.SCHistLens
518  val SCNTables = coreParams.SCNTables
519
520  val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map {
521    case ((n, cb), h) => (n, cb, h)
522  }
523  val ITTageTableInfos = coreParams.ITTageTableInfos
524  type FoldedHistoryInfo = Tuple2[Int, Int]
525  val foldedGHistInfos =
526    (TageTableInfos.map{ case (nRows, h, t) =>
527      if (h > 0)
528        Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1)))
529      else
530        Set[FoldedHistoryInfo]()
531    }.reduce(_++_).toSet ++
532    SCTableInfos.map{ case (nRows, _, h) =>
533      if (h > 0)
534        Set((h, min(log2Ceil(nRows/TageBanks), h)))
535      else
536        Set[FoldedHistoryInfo]()
537    }.reduce(_++_).toSet ++
538    ITTageTableInfos.map{ case (nRows, h, t) =>
539      if (h > 0)
540        Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1)))
541      else
542        Set[FoldedHistoryInfo]()
543    }.reduce(_++_) ++
544      Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize)))
545    ).toList
546
547
548
549  val CacheLineSize = coreParams.CacheLineSize
550  val CacheLineHalfWord = CacheLineSize / 16
551  val ExtHistoryLength = HistoryLength + 64
552  val IBufSize = coreParams.IBufSize
553  val DecodeWidth = coreParams.DecodeWidth
554  val RenameWidth = coreParams.RenameWidth
555  val CommitWidth = coreParams.CommitWidth
556  val MaxUopSize = coreParams.MaxUopSize
557  val EnableRenameSnapshot = coreParams.EnableRenameSnapshot
558  val RenameSnapshotNum = coreParams.RenameSnapshotNum
559  val FtqSize = coreParams.FtqSize
560  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
561  val IntLogicRegs = coreParams.IntLogicRegs
562  val FpLogicRegs = coreParams.FpLogicRegs
563  val VecLogicRegs = coreParams.VecLogicRegs
564  val VCONFIG_IDX = coreParams.VCONFIG_IDX
565  val IntPhyRegs = coreParams.intPreg.numEntries
566  val VfPhyRegs = coreParams.vfPreg.numEntries
567  val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs)
568  val RobSize = coreParams.RobSize
569  val RabSize = coreParams.RabSize
570  val IntRefCounterWidth = log2Ceil(RobSize)
571  val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize
572  val LoadQueueRARSize = coreParams.LoadQueueRARSize
573  val LoadQueueRAWSize = coreParams.LoadQueueRAWSize
574  val RollbackGroupSize = coreParams.RollbackGroupSize
575  val LoadQueueReplaySize = coreParams.LoadQueueReplaySize
576  val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize
577  val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks
578  val StoreQueueSize = coreParams.StoreQueueSize
579  val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks
580  val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask
581  val VlsQueueSize = coreParams.VlsQueueSize
582  val dpParams = coreParams.dpParams
583
584  def backendParams: BackendParams = coreParams.backendParams
585  def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max
586  def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max
587  val LoadPipelineWidth = coreParams.LoadPipelineWidth
588  val StorePipelineWidth = coreParams.StorePipelineWidth
589  val VecMemSrcInWidth = coreParams.VecMemSrcInWidth
590  val VecMemInstWbWidth = coreParams.VecMemInstWbWidth
591  val VecMemDispatchWidth = coreParams.VecMemDispatchWidth
592  val StoreBufferSize = coreParams.StoreBufferSize
593  val StoreBufferThreshold = coreParams.StoreBufferThreshold
594  val EnsbufferWidth = coreParams.EnsbufferWidth
595  val UncacheBufferSize = coreParams.UncacheBufferSize
596  val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward
597  val EnableFastForward = coreParams.EnableFastForward
598  val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset
599  val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset
600  val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset
601  val EnableAccurateLoadError = coreParams.EnableAccurateLoadError
602  val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding
603  val asidLen = coreParams.MMUAsidLen
604  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
605  val refillBothTlb = coreParams.refillBothTlb
606  val iwpuParam = coreParams.iwpuParameters
607  val dwpuParam = coreParams.dwpuParameters
608  val itlbParams = coreParams.itlbParameters
609  val ldtlbParams = coreParams.ldtlbParameters
610  val sttlbParams = coreParams.sttlbParameters
611  val pftlbParams = coreParams.pftlbParameters
612  val btlbParams = coreParams.btlbParameters
613  val l2tlbParams = coreParams.l2tlbParameters
614  val NumPerfCounters = coreParams.NumPerfCounters
615
616  val instBytes = if (HasCExtension) 2 else 4
617  val instOffsetBits = log2Ceil(instBytes)
618
619  val icacheParameters = coreParams.icacheParameters
620  val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
621
622  // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles
623  // for constrained LR/SC loop
624  val LRSCCycles = 64
625  // for lr storm
626  val LRSCBackOff = 8
627
628  // cache hierarchy configurations
629  val l1BusDataWidth = 256
630
631  // load violation predict
632  val ResetTimeMax2Pow = 20 //1078576
633  val ResetTimeMin2Pow = 10 //1024
634  // wait table parameters
635  val WaitTableSize = 1024
636  val MemPredPCWidth = log2Up(WaitTableSize)
637  val LWTUse2BitCounter = true
638  // store set parameters
639  val SSITSize = WaitTableSize
640  val LFSTSize = 32
641  val SSIDWidth = log2Up(LFSTSize)
642  val LFSTWidth = 4
643  val StoreSetEnable = true // LWT will be disabled if SS is enabled
644  val LFSTEnable = false
645
646  val PCntIncrStep: Int = 6
647  val numPCntHc: Int = 25
648  val numPCntPtw: Int = 19
649
650  val numCSRPCntFrontend = 8
651  val numCSRPCntCtrl     = 8
652  val numCSRPCntLsu      = 8
653  val numCSRPCntHc       = 5
654}
655