1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.cache.wpu.WPUParameters 34import coupledL2._ 35import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 36 37import scala.math.min 38 39case object XSTileKey extends Field[Seq[XSCoreParameters]] 40 41case object XSCoreParamsKey extends Field[XSCoreParameters] 42 43case class XSCoreParameters 44( 45 HasPrefetch: Boolean = false, 46 HartId: Int = 0, 47 XLEN: Int = 64, 48 VLEN: Int = 128, 49 HasMExtension: Boolean = true, 50 HasCExtension: Boolean = true, 51 HasDiv: Boolean = true, 52 HasICache: Boolean = true, 53 HasDCache: Boolean = true, 54 AddrBits: Int = 64, 55 VAddrBits: Int = 39, 56 HasFPU: Boolean = true, 57 HasCustomCSRCacheOp: Boolean = true, 58 FetchWidth: Int = 8, 59 AsidLength: Int = 16, 60 EnableBPU: Boolean = true, 61 EnableBPD: Boolean = true, 62 EnableRAS: Boolean = true, 63 EnableLB: Boolean = false, 64 EnableLoop: Boolean = true, 65 EnableSC: Boolean = true, 66 EnbaleTlbDebug: Boolean = false, 67 EnableJal: Boolean = false, 68 EnableFauFTB: Boolean = true, 69 UbtbGHRLength: Int = 4, 70 // HistoryLength: Int = 512, 71 EnableGHistDiff: Boolean = true, 72 EnableCommitGHistDiff: Boolean = true, 73 UbtbSize: Int = 256, 74 FtbSize: Int = 2048, 75 RasSize: Int = 32, 76 CacheLineSize: Int = 512, 77 FtbWays: Int = 4, 78 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 79 // Sets Hist Tag 80 // Seq(( 2048, 2, 8), 81 // ( 2048, 9, 8), 82 // ( 2048, 13, 8), 83 // ( 2048, 20, 8), 84 // ( 2048, 26, 8), 85 // ( 2048, 44, 8), 86 // ( 2048, 73, 8), 87 // ( 2048, 256, 8)), 88 Seq(( 4096, 8, 8), 89 ( 4096, 13, 8), 90 ( 4096, 32, 8), 91 ( 4096, 119, 8)), 92 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 93 // Sets Hist Tag 94 Seq(( 256, 4, 9), 95 ( 256, 8, 9), 96 ( 512, 13, 9), 97 ( 512, 16, 9), 98 ( 512, 32, 9)), 99 SCNRows: Int = 512, 100 SCNTables: Int = 4, 101 SCCtrBits: Int = 6, 102 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 103 numBr: Int = 2, 104 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 105 ((resp_in: BranchPredictionResp, p: Parameters) => { 106 val ftb = Module(new FTB()(p)) 107 val ubtb =Module(new FauFTB()(p)) 108 // val bim = Module(new BIM()(p)) 109 val tage = Module(new Tage_SC()(p)) 110 val ras = Module(new RAS()(p)) 111 val ittage = Module(new ITTage()(p)) 112 val preds = Seq(ubtb, tage, ftb, ittage, ras) 113 preds.map(_.io := DontCare) 114 115 // ubtb.io.resp_in(0) := resp_in 116 // bim.io.resp_in(0) := ubtb.io.resp 117 // btb.io.resp_in(0) := bim.io.resp 118 // tage.io.resp_in(0) := btb.io.resp 119 // loop.io.resp_in(0) := tage.io.resp 120 ubtb.io.in.bits.resp_in(0) := resp_in 121 tage.io.in.bits.resp_in(0) := ubtb.io.out 122 ftb.io.in.bits.resp_in(0) := tage.io.out 123 ittage.io.in.bits.resp_in(0) := ftb.io.out 124 ras.io.in.bits.resp_in(0) := ittage.io.out 125 126 (preds, ras.io.out) 127 }), 128 IBufSize: Int = 48, 129 DecodeWidth: Int = 6, 130 RenameWidth: Int = 6, 131 CommitWidth: Int = 6, 132 EnableRenameSnapshot: Boolean = true, 133 RenameSnapshotNum: Int = 4, 134 FtqSize: Int = 64, 135 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 136 IssQueSize: Int = 16, 137 NRPhyRegs: Int = 192, 138 VirtualLoadQueueSize: Int = 80, 139 LoadQueueRARSize: Int = 80, 140 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 141 RollbackGroupSize: Int = 8, 142 LoadQueueReplaySize: Int = 72, 143 LoadUncacheBufferSize: Int = 20, 144 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 145 StoreQueueSize: Int = 64, 146 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 147 StoreQueueForwardWithMask: Boolean = true, 148 VlsQueueSize: Int = 8, 149 RobSize: Int = 256, 150 dpParams: DispatchParameters = DispatchParameters( 151 IntDqSize = 16, 152 FpDqSize = 16, 153 LsDqSize = 16, 154 IntDqDeqWidth = 4, 155 FpDqDeqWidth = 4, 156 LsDqDeqWidth = 4 157 ), 158 exuParameters: ExuParameters = ExuParameters( 159 JmpCnt = 1, 160 AluCnt = 4, 161 MulCnt = 0, 162 MduCnt = 2, 163 FmacCnt = 4, 164 FmiscCnt = 2, 165 FmiscDivSqrtCnt = 0, 166 LduCnt = 2, 167 StuCnt = 2 168 ), 169 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 170 LoadPipelineWidth: Int = 2, 171 StorePipelineWidth: Int = 2, 172 VecMemSrcInWidth: Int = 2, 173 VecMemInstWbWidth: Int = 1, 174 VecMemDispatchWidth: Int = 1, 175 StoreBufferSize: Int = 16, 176 StoreBufferThreshold: Int = 7, 177 EnsbufferWidth: Int = 2, 178 UncacheBufferSize: Int = 4, 179 EnableLoadToLoadForward: Boolean = true, 180 EnableFastForward: Boolean = true, 181 EnableLdVioCheckAfterReset: Boolean = true, 182 EnableSoftPrefetchAfterReset: Boolean = true, 183 EnableCacheErrorAfterReset: Boolean = true, 184 EnableAccurateLoadError: Boolean = true, 185 EnableUncacheWriteOutstanding: Boolean = false, 186 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 187 ReSelectLen: Int = 7, // load replay queue replay select counter len 188 iwpuParameters: WPUParameters = WPUParameters( 189 enWPU = false, 190 algoName = "mmru", 191 isICache = true, 192 ), 193 dwpuParameters: WPUParameters = WPUParameters( 194 enWPU = false, 195 algoName = "mmru", 196 enCfPred = false, 197 isICache = false, 198 ), 199 itlbParameters: TLBParameters = TLBParameters( 200 name = "itlb", 201 fetchi = true, 202 useDmode = false, 203 normalNWays = 32, 204 normalReplacer = Some("plru"), 205 superNWays = 4, 206 superReplacer = Some("plru") 207 ), 208 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 209 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 210 ldtlbParameters: TLBParameters = TLBParameters( 211 name = "ldtlb", 212 normalNSets = 64, 213 normalNWays = 1, 214 normalAssociative = "sa", 215 normalReplacer = Some("setplru"), 216 superNWays = 16, 217 normalAsVictim = true, 218 outReplace = false, 219 partialStaticPMP = true, 220 outsideRecvFlush = true, 221 saveLevel = true 222 ), 223 sttlbParameters: TLBParameters = TLBParameters( 224 name = "sttlb", 225 normalNSets = 64, 226 normalNWays = 1, 227 normalAssociative = "sa", 228 normalReplacer = Some("setplru"), 229 superNWays = 16, 230 normalAsVictim = true, 231 outReplace = false, 232 partialStaticPMP = true, 233 outsideRecvFlush = true, 234 saveLevel = true 235 ), 236 pftlbParameters: TLBParameters = TLBParameters( 237 name = "pftlb", 238 normalNSets = 64, 239 normalNWays = 1, 240 normalAssociative = "sa", 241 normalReplacer = Some("setplru"), 242 superNWays = 16, 243 normalAsVictim = true, 244 outReplace = false, 245 partialStaticPMP = true, 246 outsideRecvFlush = true, 247 saveLevel = true 248 ), 249 refillBothTlb: Boolean = false, 250 btlbParameters: TLBParameters = TLBParameters( 251 name = "btlb", 252 normalNSets = 1, 253 normalNWays = 64, 254 superNWays = 4, 255 ), 256 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 257 NumPerfCounters: Int = 16, 258 icacheParameters: ICacheParameters = ICacheParameters( 259 tagECC = Some("parity"), 260 dataECC = Some("parity"), 261 replacer = Some("setplru"), 262 nMissEntries = 2, 263 nProbeEntries = 2, 264 nPrefetchEntries = 12, 265 nPrefBufferEntries = 32, 266 hasPrefetch = true, 267 ), 268 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 269 tagECC = Some("secded"), 270 dataECC = Some("secded"), 271 replacer = Some("setplru"), 272 nMissEntries = 16, 273 nProbeEntries = 8, 274 nReleaseEntries = 18 275 )), 276 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 277 name = "l2", 278 ways = 8, 279 sets = 1024, // default 512KB L2 280 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 281 )), 282 L2NBanks: Int = 1, 283 usePTWRepeater: Boolean = false, 284 softTLB: Boolean = false, // dpi-c l1tlb debug only 285 softPTW: Boolean = false, // dpi-c l2tlb debug only 286 softPTWDelay: Int = 1 287){ 288 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 289 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 290 291 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 292 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 293 294 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 295 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 296 297 val fpExuConfigs = 298 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 299 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 300 301 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 302} 303 304case object DebugOptionsKey extends Field[DebugOptions] 305 306case class DebugOptions 307( 308 FPGAPlatform: Boolean = false, 309 EnableDifftest: Boolean = false, 310 AlwaysBasicDiff: Boolean = true, 311 EnableDebug: Boolean = false, 312 EnablePerfDebug: Boolean = true, 313 UseDRAMSim: Boolean = false, 314 EnableConstantin: Boolean = false, 315 EnableChiselDB: Boolean = false, 316 AlwaysBasicDB: Boolean = true, 317 EnableRollingDB: Boolean = false 318) 319 320trait HasXSParameter { 321 322 implicit val p: Parameters 323 324 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 325 326 val coreParams = p(XSCoreParamsKey) 327 val env = p(DebugOptionsKey) 328 329 val XLEN = coreParams.XLEN 330 val VLEN = coreParams.VLEN 331 val minFLen = 32 332 val fLen = 64 333 def xLen = XLEN 334 335 val HasMExtension = coreParams.HasMExtension 336 val HasCExtension = coreParams.HasCExtension 337 val HasDiv = coreParams.HasDiv 338 val HasIcache = coreParams.HasICache 339 val HasDcache = coreParams.HasDCache 340 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 341 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 342 val AsidLength = coreParams.AsidLength 343 val ReSelectLen = coreParams.ReSelectLen 344 val AddrBytes = AddrBits / 8 // unused 345 val DataBits = XLEN 346 val DataBytes = DataBits / 8 347 val VDataBytes = VLEN / 8 348 val HasFPU = coreParams.HasFPU 349 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 350 val FetchWidth = coreParams.FetchWidth 351 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 352 val EnableBPU = coreParams.EnableBPU 353 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 354 val EnableRAS = coreParams.EnableRAS 355 val EnableLB = coreParams.EnableLB 356 val EnableLoop = coreParams.EnableLoop 357 val EnableSC = coreParams.EnableSC 358 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 359 val HistoryLength = coreParams.HistoryLength 360 val EnableGHistDiff = coreParams.EnableGHistDiff 361 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 362 val UbtbGHRLength = coreParams.UbtbGHRLength 363 val UbtbSize = coreParams.UbtbSize 364 val EnableFauFTB = coreParams.EnableFauFTB 365 val FtbSize = coreParams.FtbSize 366 val FtbWays = coreParams.FtbWays 367 val RasSize = coreParams.RasSize 368 369 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 370 coreParams.branchPredictor(resp_in, p) 371 } 372 val numBr = coreParams.numBr 373 val TageTableInfos = coreParams.TageTableInfos 374 val TageBanks = coreParams.numBr 375 val SCNRows = coreParams.SCNRows 376 val SCCtrBits = coreParams.SCCtrBits 377 val SCHistLens = coreParams.SCHistLens 378 val SCNTables = coreParams.SCNTables 379 380 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 381 case ((n, cb), h) => (n, cb, h) 382 } 383 val ITTageTableInfos = coreParams.ITTageTableInfos 384 type FoldedHistoryInfo = Tuple2[Int, Int] 385 val foldedGHistInfos = 386 (TageTableInfos.map{ case (nRows, h, t) => 387 if (h > 0) 388 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 389 else 390 Set[FoldedHistoryInfo]() 391 }.reduce(_++_).toSet ++ 392 SCTableInfos.map{ case (nRows, _, h) => 393 if (h > 0) 394 Set((h, min(log2Ceil(nRows/TageBanks), h))) 395 else 396 Set[FoldedHistoryInfo]() 397 }.reduce(_++_).toSet ++ 398 ITTageTableInfos.map{ case (nRows, h, t) => 399 if (h > 0) 400 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 401 else 402 Set[FoldedHistoryInfo]() 403 }.reduce(_++_) ++ 404 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 405 ).toList 406 407 408 409 val CacheLineSize = coreParams.CacheLineSize 410 val CacheLineHalfWord = CacheLineSize / 16 411 val ExtHistoryLength = HistoryLength + 64 412 val IBufSize = coreParams.IBufSize 413 val DecodeWidth = coreParams.DecodeWidth 414 val RenameWidth = coreParams.RenameWidth 415 val CommitWidth = coreParams.CommitWidth 416 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 417 val RenameSnapshotNum = coreParams.RenameSnapshotNum 418 val FtqSize = coreParams.FtqSize 419 val IssQueSize = coreParams.IssQueSize 420 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 421 val NRPhyRegs = coreParams.NRPhyRegs 422 val PhyRegIdxWidth = log2Up(NRPhyRegs) 423 val RobSize = coreParams.RobSize 424 val IntRefCounterWidth = log2Ceil(RobSize) 425 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 426 val LoadQueueRARSize = coreParams.LoadQueueRARSize 427 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 428 val RollbackGroupSize = coreParams.RollbackGroupSize 429 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 430 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 431 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 432 val StoreQueueSize = coreParams.StoreQueueSize 433 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 434 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 435 val VlsQueueSize = coreParams.VlsQueueSize 436 val dpParams = coreParams.dpParams 437 val exuParameters = coreParams.exuParameters 438 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 439 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 440 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 441 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 442 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 443 val LoadPipelineWidth = coreParams.LoadPipelineWidth 444 val StorePipelineWidth = coreParams.StorePipelineWidth 445 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 446 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 447 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 448 val StoreBufferSize = coreParams.StoreBufferSize 449 val StoreBufferThreshold = coreParams.StoreBufferThreshold 450 val EnsbufferWidth = coreParams.EnsbufferWidth 451 val UncacheBufferSize = coreParams.UncacheBufferSize 452 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 453 val EnableFastForward = coreParams.EnableFastForward 454 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 455 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 456 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 457 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 458 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 459 val asidLen = coreParams.MMUAsidLen 460 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 461 val refillBothTlb = coreParams.refillBothTlb 462 val iwpuParam = coreParams.iwpuParameters 463 val dwpuParam = coreParams.dwpuParameters 464 val itlbParams = coreParams.itlbParameters 465 val ldtlbParams = coreParams.ldtlbParameters 466 val sttlbParams = coreParams.sttlbParameters 467 val pftlbParams = coreParams.pftlbParameters 468 val btlbParams = coreParams.btlbParameters 469 val l2tlbParams = coreParams.l2tlbParameters 470 val NumPerfCounters = coreParams.NumPerfCounters 471 472 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 473 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 474 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 475 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 476 477 val instBytes = if (HasCExtension) 2 else 4 478 val instOffsetBits = log2Ceil(instBytes) 479 480 val icacheParameters = coreParams.icacheParameters 481 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 482 483 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 484 // for constrained LR/SC loop 485 val LRSCCycles = 64 486 // for lr storm 487 val LRSCBackOff = 8 488 489 // cache hierarchy configurations 490 val l1BusDataWidth = 256 491 492 // load violation predict 493 val ResetTimeMax2Pow = 20 //1078576 494 val ResetTimeMin2Pow = 10 //1024 495 // wait table parameters 496 val WaitTableSize = 1024 497 val MemPredPCWidth = log2Up(WaitTableSize) 498 val LWTUse2BitCounter = true 499 // store set parameters 500 val SSITSize = WaitTableSize 501 val LFSTSize = 32 502 val SSIDWidth = log2Up(LFSTSize) 503 val LFSTWidth = 4 504 val StoreSetEnable = true // LWT will be disabled if SS is enabled 505 val LFSTEnable = false 506 val loadExuConfigs = coreParams.loadExuConfigs 507 val storeExuConfigs = coreParams.storeExuConfigs 508 509 val intExuConfigs = coreParams.intExuConfigs 510 511 val fpExuConfigs = coreParams.fpExuConfigs 512 513 val exuConfigs = coreParams.exuConfigs 514 515 val PCntIncrStep: Int = 6 516 val numPCntHc: Int = 25 517 val numPCntPtw: Int = 19 518 519 val numCSRPCntFrontend = 8 520 val numCSRPCntCtrl = 8 521 val numCSRPCntLsu = 8 522 val numCSRPCntHc = 5 523} 524