1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 PathHistoryLength: Int = 16, 59 BtbSize: Int = 2048, 60 JbtacSize: Int = 1024, 61 JbtacBanks: Int = 8, 62 RasSize: Int = 32, 63 CacheLineSize: Int = 512, 64 UBtbWays: Int = 16, 65 BtbWays: Int = 2, 66 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 67 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 68 // val loop = Module(new LoopPredictor) 69 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 70 // else Module(new Tage) } 71 // else { Module(new FakeTage) }) 72 val ftb = Module(new FTB()(p)) 73 val ubtb = Module(new MicroBTB()(p)) 74 val bim = Module(new BIM()(p)) 75 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 76 val ras = Module(new RAS()(p)) 77 val ittage = Module(new ITTage()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 95 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 96 97 (preds, ras.io.out.resp) 98 }), 99 100 101 EnableL1plusPrefetcher: Boolean = true, 102 IBufSize: Int = 48, 103 DecodeWidth: Int = 6, 104 RenameWidth: Int = 6, 105 CommitWidth: Int = 6, 106 BrqSize: Int = 32, 107 FtqSize: Int = 64, 108 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 109 IssQueSize: Int = 16, 110 NRPhyRegs: Int = 160, 111 NRIntReadPorts: Int = 14, 112 NRIntWritePorts: Int = 8, 113 NRFpReadPorts: Int = 14, 114 NRFpWritePorts: Int = 8, 115 LoadQueueSize: Int = 64, 116 StoreQueueSize: Int = 48, 117 RoqSize: Int = 192, 118 EnableIntMoveElim: Boolean = true, 119 IntRefCounterWidth: Int = 2, 120 dpParams: DispatchParameters = DispatchParameters( 121 IntDqSize = 16, 122 FpDqSize = 16, 123 LsDqSize = 16, 124 IntDqDeqWidth = 4, 125 FpDqDeqWidth = 4, 126 LsDqDeqWidth = 4 127 ), 128 exuParameters: ExuParameters = ExuParameters( 129 JmpCnt = 1, 130 AluCnt = 4, 131 MulCnt = 0, 132 MduCnt = 2, 133 FmacCnt = 4, 134 FmiscCnt = 2, 135 FmiscDivSqrtCnt = 0, 136 LduCnt = 2, 137 StuCnt = 2 138 ), 139 LoadPipelineWidth: Int = 2, 140 StorePipelineWidth: Int = 2, 141 StoreBufferSize: Int = 16, 142 StoreBufferThreshold: Int = 7, 143 EnableFastForward: Boolean = true, 144 RefillSize: Int = 512, 145 itlbParameters: TLBParameters = TLBParameters( 146 name = "itlb", 147 fetchi = true, 148 useDmode = false, 149 sameCycle = true, 150 normalNWays = 32, 151 normalReplacer = Some("plru"), 152 superNWays = 4, 153 superReplacer = Some("plru"), 154 shouldBlock = true 155 ), 156 ldtlbParameters: TLBParameters = TLBParameters( 157 name = "ldtlb", 158 normalNSets = 128, 159 normalNWays = 1, 160 normalAssociative = "sa", 161 normalReplacer = Some("setplru"), 162 superNWays = 8, 163 normalAsVictim = true, 164 outReplace = true 165 ), 166 sttlbParameters: TLBParameters = TLBParameters( 167 name = "sttlb", 168 normalNSets = 128, 169 normalNWays = 1, 170 normalAssociative = "sa", 171 normalReplacer = Some("setplru"), 172 superNWays = 8, 173 normalAsVictim = true, 174 outReplace = true 175 ), 176 refillBothTlb: Boolean = false, 177 btlbParameters: TLBParameters = TLBParameters( 178 name = "btlb", 179 normalNSets = 1, 180 normalNWays = 64, 181 superNWays = 4, 182 ), 183 useBTlb: Boolean = false, 184 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 185 NumPerfCounters: Int = 16, 186 icacheParameters: ICacheParameters = ICacheParameters( 187 tagECC = Some("parity"), 188 dataECC = Some("parity"), 189 replacer = Some("setplru"), 190 nMissEntries = 2 191 ), 192 dcacheParameters: DCacheParameters = DCacheParameters( 193 tagECC = Some("secded"), 194 dataECC = Some("secded"), 195 replacer = Some("setplru"), 196 nMissEntries = 16, 197 nProbeEntries = 16, 198 nReleaseEntries = 16, 199 nStoreReplayEntries = 16 200 ), 201 L2CacheParams: HCCacheParameters = HCCacheParameters( 202 name = "l2", 203 level = 2, 204 ways = 8, 205 sets = 1024, // default 512KB L2 206 prefetch = Some(huancun.prefetch.BOPParameters()) 207 ), 208 usePTWRepeater: Boolean = false, 209 useFakePTW: Boolean = false, 210 useFakeDCache: Boolean = false, 211 useFakeL1plusCache: Boolean = false, 212 useFakeL2Cache: Boolean = false 213){ 214 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 215 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 216 217 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 218 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 219 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 220 221 val fpExuConfigs = 222 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 223 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 224 225 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 226} 227 228case object DebugOptionsKey extends Field[DebugOptions] 229 230case class DebugOptions 231( 232 FPGAPlatform: Boolean = true, 233 EnableDebug: Boolean = true, 234 EnablePerfDebug: Boolean = true, 235 UseDRAMSim: Boolean = false 236) 237 238trait HasXSParameter { 239 240 implicit val p: Parameters 241 242 val coreParams = p(XSCoreParamsKey) 243 val env = p(DebugOptionsKey) 244 245 val XLEN = coreParams.XLEN 246 val hardId = coreParams.HartId 247 val minFLen = 32 248 val fLen = 64 249 def xLen = XLEN 250 251 val HasMExtension = coreParams.HasMExtension 252 val HasCExtension = coreParams.HasCExtension 253 val HasDiv = coreParams.HasDiv 254 val HasIcache = coreParams.HasICache 255 val HasDcache = coreParams.HasDCache 256 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 257 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 258 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 259 val AddrBytes = AddrBits / 8 // unused 260 val DataBits = XLEN 261 val DataBytes = DataBits / 8 262 val HasFPU = coreParams.HasFPU 263 val FetchWidth = coreParams.FetchWidth 264 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 265 val EnableBPU = coreParams.EnableBPU 266 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 267 val EnableRAS = coreParams.EnableRAS 268 val EnableLB = coreParams.EnableLB 269 val EnableLoop = coreParams.EnableLoop 270 val EnableSC = coreParams.EnableSC 271 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 272 val HistoryLength = coreParams.HistoryLength 273 val PathHistoryLength = coreParams.PathHistoryLength 274 val BtbSize = coreParams.BtbSize 275 // val BtbWays = 4 276 val BtbBanks = PredictWidth 277 // val BtbSets = BtbSize / BtbWays 278 val JbtacSize = coreParams.JbtacSize 279 val JbtacBanks = coreParams.JbtacBanks 280 val RasSize = coreParams.RasSize 281 282 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 283 coreParams.branchPredictor(resp_in, p, enableSC) 284 } 285 286 val CacheLineSize = coreParams.CacheLineSize 287 val CacheLineHalfWord = CacheLineSize / 16 288 val ExtHistoryLength = HistoryLength + 64 289 val UBtbWays = coreParams.UBtbWays 290 val BtbWays = coreParams.BtbWays 291 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 292 val IBufSize = coreParams.IBufSize 293 val DecodeWidth = coreParams.DecodeWidth 294 val RenameWidth = coreParams.RenameWidth 295 val CommitWidth = coreParams.CommitWidth 296 val BrqSize = coreParams.BrqSize 297 val FtqSize = coreParams.FtqSize 298 val IssQueSize = coreParams.IssQueSize 299 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 300 val BrTagWidth = log2Up(BrqSize) 301 val NRPhyRegs = coreParams.NRPhyRegs 302 val PhyRegIdxWidth = log2Up(NRPhyRegs) 303 val RoqSize = coreParams.RoqSize 304 val EnableIntMoveElim = coreParams.EnableIntMoveElim 305 val IntRefCounterWidth = coreParams.IntRefCounterWidth 306 val StdFreeListSize = NRPhyRegs - 32 307 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 308 val MEFreeListSize = NRPhyRegs 309 val LoadQueueSize = coreParams.LoadQueueSize 310 val StoreQueueSize = coreParams.StoreQueueSize 311 val dpParams = coreParams.dpParams 312 val exuParameters = coreParams.exuParameters 313 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 314 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 315 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 316 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 317 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 318 val LoadPipelineWidth = coreParams.LoadPipelineWidth 319 val StorePipelineWidth = coreParams.StorePipelineWidth 320 val StoreBufferSize = coreParams.StoreBufferSize 321 val StoreBufferThreshold = coreParams.StoreBufferThreshold 322 val EnableFastForward = coreParams.EnableFastForward 323 val RefillSize = coreParams.RefillSize 324 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 325 val refillBothTlb = coreParams.refillBothTlb 326 val useBTlb = coreParams.useBTlb 327 val itlbParams = coreParams.itlbParameters 328 val ldtlbParams = coreParams.ldtlbParameters 329 val sttlbParams = coreParams.sttlbParameters 330 val btlbParams = coreParams.btlbParameters 331 val l2tlbParams = coreParams.l2tlbParameters 332 val NumPerfCounters = coreParams.NumPerfCounters 333 334 val instBytes = if (HasCExtension) 2 else 4 335 val instOffsetBits = log2Ceil(instBytes) 336 337 val icacheParameters = coreParams.icacheParameters 338 val dcacheParameters = coreParams.dcacheParameters 339 340 val LRSCCycles = 100 341 342 343 // cache hierarchy configurations 344 val l1BusDataWidth = 256 345 346 val useFakeDCache = coreParams.useFakeDCache 347 val useFakePTW = coreParams.useFakePTW 348 val useFakeL1plusCache = coreParams.useFakeL1plusCache 349 // L2 configurations 350 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 351 val L1BusWidth = 256 352 val L2BlockSize = 64 353 354 // L3 configurations 355 val L2BusWidth = 256 356 357 // load violation predict 358 val ResetTimeMax2Pow = 20 //1078576 359 val ResetTimeMin2Pow = 10 //1024 360 // wait table parameters 361 val WaitTableSize = 1024 362 val MemPredPCWidth = log2Up(WaitTableSize) 363 val LWTUse2BitCounter = true 364 // store set parameters 365 val SSITSize = WaitTableSize 366 val LFSTSize = 32 367 val SSIDWidth = log2Up(LFSTSize) 368 val LFSTWidth = 4 369 val StoreSetEnable = true // LWT will be disabled if SS is enabled 370 371 val loadExuConfigs = coreParams.loadExuConfigs 372 val storeExuConfigs = coreParams.storeExuConfigs 373 374 val intExuConfigs = coreParams.intExuConfigs 375 376 val fpExuConfigs = coreParams.fpExuConfigs 377 378 val exuConfigs = coreParams.exuConfigs 379 380} 381