1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import freechips.rocketchip.diplomacy.AddressSet 29 30case object XSCoreParamsKey extends Field[XSCoreParameters] 31 32case class XSCoreParameters 33( 34 HasPrefetch: Boolean = false, 35 HartId: Int = 0, 36 XLEN: Int = 64, 37 HasMExtension: Boolean = true, 38 HasCExtension: Boolean = true, 39 HasDiv: Boolean = true, 40 HasICache: Boolean = true, 41 HasDCache: Boolean = true, 42 AddrBits: Int = 64, 43 VAddrBits: Int = 39, 44 PAddrBits: Int = 40, 45 HasFPU: Boolean = true, 46 FetchWidth: Int = 8, 47 EnableBPU: Boolean = true, 48 EnableBPD: Boolean = true, 49 EnableRAS: Boolean = true, 50 EnableLB: Boolean = false, 51 EnableLoop: Boolean = true, 52 EnableSC: Boolean = true, 53 EnbaleTlbDebug: Boolean = false, 54 EnableJal: Boolean = false, 55 EnableUBTB: Boolean = true, 56 HistoryLength: Int = 64, 57 BtbSize: Int = 2048, 58 JbtacSize: Int = 1024, 59 JbtacBanks: Int = 8, 60 RasSize: Int = 16, 61 CacheLineSize: Int = 512, 62 UBtbWays: Int = 16, 63 BtbWays: Int = 2, 64 65 EnableL1plusPrefetcher: Boolean = true, 66 IBufSize: Int = 48, 67 DecodeWidth: Int = 6, 68 RenameWidth: Int = 6, 69 CommitWidth: Int = 6, 70 BrqSize: Int = 32, 71 FtqSize: Int = 48, 72 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 73 IssQueSize: Int = 16, 74 NRPhyRegs: Int = 160, 75 NRIntReadPorts: Int = 14, 76 NRIntWritePorts: Int = 8, 77 NRFpReadPorts: Int = 14, 78 NRFpWritePorts: Int = 8, 79 LoadQueueSize: Int = 64, 80 StoreQueueSize: Int = 48, 81 RoqSize: Int = 192, 82 EnableIntMoveElim: Boolean = true, 83 IntRefCounterWidth: Int = 2, 84 dpParams: DispatchParameters = DispatchParameters( 85 IntDqSize = 16, 86 FpDqSize = 16, 87 LsDqSize = 16, 88 IntDqDeqWidth = 4, 89 FpDqDeqWidth = 4, 90 LsDqDeqWidth = 4 91 ), 92 exuParameters: ExuParameters = ExuParameters( 93 JmpCnt = 1, 94 AluCnt = 4, 95 MulCnt = 0, 96 MduCnt = 2, 97 FmacCnt = 4, 98 FmiscCnt = 2, 99 FmiscDivSqrtCnt = 0, 100 LduCnt = 2, 101 StuCnt = 2 102 ), 103 LoadPipelineWidth: Int = 2, 104 StorePipelineWidth: Int = 2, 105 StoreBufferSize: Int = 16, 106 StoreBufferThreshold: Int = 7, 107 RefillSize: Int = 512, 108 TlbEntrySize: Int = 8, 109 TlbSPEntrySize: Int = 2, 110 BTlbEntrySize: Int = 64, 111 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 112 PtwSPEntrySize: Int = 16, 113 PtwL1EntrySize: Int = 16, 114 PtwL2EntrySize: Int = 256, //(256 * 8) 115 PtwMissQueueSize: Int = 8, 116 NumPerfCounters: Int = 16, 117 icacheParameters: ICacheParameters = ICacheParameters( 118 tagECC = Some("parity"), 119 dataECC = Some("parity"), 120 replacer = Some("setplru"), 121 nMissEntries = 2 122 ), 123 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 124 tagECC = Some("secded"), 125 dataECC = Some("secded"), 126 replacer = Some("setplru"), 127 nMissEntries = 8 128 ), 129 dcacheParameters: DCacheParameters = DCacheParameters( 130 tagECC = Some("secded"), 131 dataECC = Some("secded"), 132 replacer = Some("setplru"), 133 nMissEntries = 16, 134 nProbeEntries = 16, 135 nReleaseEntries = 16, 136 nStoreReplayEntries = 16 137 ), 138 L2Size: Int = 512 * 1024, // 512KB 139 L2NWays: Int = 8, 140 usePTWRepeater: Boolean = false, 141 useFakePTW: Boolean = false, 142 useFakeDCache: Boolean = false, 143 useFakeL1plusCache: Boolean = false, 144 useFakeL2Cache: Boolean = false 145){ 146 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 147 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 148 149 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 150 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 151 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 152 153 val fpExuConfigs = 154 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 155 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 156 157 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 158} 159 160case object DebugOptionsKey extends Field[DebugOptions] 161 162case class DebugOptions 163( 164 FPGAPlatform: Boolean = true, 165 EnableDebug: Boolean = true, 166 EnablePerfDebug: Boolean = true, 167 UseDRAMSim: Boolean = false 168) 169 170trait HasXSParameter { 171 172 implicit val p: Parameters 173 174 val coreParams = p(XSCoreParamsKey) 175 val env = p(DebugOptionsKey) 176 177 val XLEN = coreParams.XLEN 178 val hardId = coreParams.HartId 179 val minFLen = 32 180 val fLen = 64 181 def xLen = XLEN 182 183 val HasMExtension = coreParams.HasMExtension 184 val HasCExtension = coreParams.HasCExtension 185 val HasDiv = coreParams.HasDiv 186 val HasIcache = coreParams.HasICache 187 val HasDcache = coreParams.HasDCache 188 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 189 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 190 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 191 val AddrBytes = AddrBits / 8 // unused 192 val DataBits = XLEN 193 val DataBytes = DataBits / 8 194 val HasFPU = coreParams.HasFPU 195 val FetchWidth = coreParams.FetchWidth 196 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 197 val EnableBPU = coreParams.EnableBPU 198 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 199 val EnableRAS = coreParams.EnableRAS 200 val EnableLB = coreParams.EnableLB 201 val EnableLoop = coreParams.EnableLoop 202 val EnableSC = coreParams.EnableSC 203 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 204 val HistoryLength = coreParams.HistoryLength 205 val BtbSize = coreParams.BtbSize 206 // val BtbWays = 4 207 val BtbBanks = PredictWidth 208 // val BtbSets = BtbSize / BtbWays 209 val JbtacSize = coreParams.JbtacSize 210 val JbtacBanks = coreParams.JbtacBanks 211 val RasSize = coreParams.RasSize 212 val CacheLineSize = coreParams.CacheLineSize 213 val CacheLineHalfWord = CacheLineSize / 16 214 val ExtHistoryLength = HistoryLength + 64 215 val UBtbWays = coreParams.UBtbWays 216 val BtbWays = coreParams.BtbWays 217 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 218 val IBufSize = coreParams.IBufSize 219 val DecodeWidth = coreParams.DecodeWidth 220 val RenameWidth = coreParams.RenameWidth 221 val CommitWidth = coreParams.CommitWidth 222 val BrqSize = coreParams.BrqSize 223 val FtqSize = coreParams.FtqSize 224 val IssQueSize = coreParams.IssQueSize 225 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 226 val BrTagWidth = log2Up(BrqSize) 227 val NRPhyRegs = coreParams.NRPhyRegs 228 val PhyRegIdxWidth = log2Up(NRPhyRegs) 229 val RoqSize = coreParams.RoqSize 230 val EnableIntMoveElim = coreParams.EnableIntMoveElim 231 val IntRefCounterWidth = coreParams.IntRefCounterWidth 232 val StdFreeListSize = NRPhyRegs - 32 233 val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 234 val LoadQueueSize = coreParams.LoadQueueSize 235 val StoreQueueSize = coreParams.StoreQueueSize 236 val dpParams = coreParams.dpParams 237 val exuParameters = coreParams.exuParameters 238 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 239 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 240 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 241 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 242 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 243 val LoadPipelineWidth = coreParams.LoadPipelineWidth 244 val StorePipelineWidth = coreParams.StorePipelineWidth 245 val StoreBufferSize = coreParams.StoreBufferSize 246 val StoreBufferThreshold = coreParams.StoreBufferThreshold 247 val RefillSize = coreParams.RefillSize 248 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 249 val TlbEntrySize = coreParams.TlbEntrySize 250 val TlbSPEntrySize = coreParams.TlbSPEntrySize 251 val BTlbEntrySize = coreParams.BTlbEntrySize 252 val PtwL3EntrySize = coreParams.PtwL3EntrySize 253 val PtwSPEntrySize = coreParams.PtwSPEntrySize 254 val PtwL1EntrySize = coreParams.PtwL1EntrySize 255 val PtwL2EntrySize = coreParams.PtwL2EntrySize 256 val PtwMissQueueSize = coreParams.PtwMissQueueSize 257 val NumPerfCounters = coreParams.NumPerfCounters 258 259 val instBytes = if (HasCExtension) 2 else 4 260 val instOffsetBits = log2Ceil(instBytes) 261 262 val icacheParameters = coreParams.icacheParameters 263 val l1plusCacheParameters = coreParams.l1plusCacheParameters 264 val dcacheParameters = coreParams.dcacheParameters 265 266 val LRSCCycles = 100 267 268 269 // cache hierarchy configurations 270 val l1BusDataWidth = 256 271 272 val usePTWRepeater = coreParams.usePTWRepeater 273 val useFakeDCache = coreParams.useFakeDCache 274 val useFakePTW = coreParams.useFakePTW 275 val useFakeL1plusCache = coreParams.useFakeL1plusCache 276 // L2 configurations 277 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 278 val L1BusWidth = 256 279 val L2Size = coreParams.L2Size 280 val L2BlockSize = 64 281 val L2NWays = coreParams.L2NWays 282 val L2NSets = L2Size / L2BlockSize / L2NWays 283 284 // L3 configurations 285 val L2BusWidth = 256 286 287 // icache prefetcher 288 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 289 enable = true, 290 _type = "stream", 291 streamParams = StreamPrefetchParameters( 292 streamCnt = 2, 293 streamSize = 4, 294 ageWidth = 4, 295 blockBytes = l1plusCacheParameters.blockBytes, 296 reallocStreamOnMissInstantly = true, 297 cacheName = "icache" 298 ) 299 ) 300 301 // dcache prefetcher 302 val l2PrefetcherParameters = L2PrefetcherParameters( 303 enable = true, 304 _type = "bop", // "stream" or "bop" 305 streamParams = StreamPrefetchParameters( 306 streamCnt = 4, 307 streamSize = 4, 308 ageWidth = 4, 309 blockBytes = L2BlockSize, 310 reallocStreamOnMissInstantly = true, 311 cacheName = "dcache" 312 ), 313 bopParams = BOPParameters( 314 rrTableEntries = 256, 315 rrTagBits = 12, 316 scoreBits = 5, 317 roundMax = 50, 318 badScore = 1, 319 blockBytes = L2BlockSize, 320 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 321 ), 322 ) 323 324 // load violation predict 325 val ResetTimeMax2Pow = 20 //1078576 326 val ResetTimeMin2Pow = 10 //1024 327 // wait table parameters 328 val WaitTableSize = 1024 329 val MemPredPCWidth = log2Up(WaitTableSize) 330 val LWTUse2BitCounter = true 331 // store set parameters 332 val SSITSize = WaitTableSize 333 val LFSTSize = 32 334 val SSIDWidth = log2Up(LFSTSize) 335 val LFSTWidth = 4 336 val StoreSetEnable = true // LWT will be disabled if SS is enabled 337 338 val loadExuConfigs = coreParams.loadExuConfigs 339 val storeExuConfigs = coreParams.storeExuConfigs 340 341 val intExuConfigs = coreParams.intExuConfigs 342 343 val fpExuConfigs = coreParams.fpExuConfigs 344 345 val exuConfigs = coreParams.exuConfigs 346 347} 348