1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 CacheLineSize: Int = 512, 91 FtbWays: Int = 4, 92 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 93 // Sets Hist Tag 94 // Seq(( 2048, 2, 8), 95 // ( 2048, 9, 8), 96 // ( 2048, 13, 8), 97 // ( 2048, 20, 8), 98 // ( 2048, 26, 8), 99 // ( 2048, 44, 8), 100 // ( 2048, 73, 8), 101 // ( 2048, 256, 8)), 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 119 ((resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val ubtb =Module(new FauFTB()(p)) 122 // val bim = Module(new BIM()(p)) 123 val tage = Module(new Tage_SC()(p)) 124 val ras = Module(new RAS()(p)) 125 val ittage = Module(new ITTage()(p)) 126 val preds = Seq(ubtb, tage, ftb, ittage, ras) 127 preds.map(_.io := DontCare) 128 129 // ubtb.io.resp_in(0) := resp_in 130 // bim.io.resp_in(0) := ubtb.io.resp 131 // btb.io.resp_in(0) := bim.io.resp 132 // tage.io.resp_in(0) := btb.io.resp 133 // loop.io.resp_in(0) := tage.io.resp 134 ubtb.io.in.bits.resp_in(0) := resp_in 135 tage.io.in.bits.resp_in(0) := ubtb.io.out 136 ftb.io.in.bits.resp_in(0) := tage.io.out 137 ittage.io.in.bits.resp_in(0) := ftb.io.out 138 ras.io.in.bits.resp_in(0) := ittage.io.out 139 140 (preds, ras.io.out) 141 }), 142 IBufSize: Int = 48, 143 DecodeWidth: Int = 6, 144 RenameWidth: Int = 6, 145 CommitWidth: Int = 6, 146 MaxUopSize: Int = 65, 147 EnableRenameSnapshot: Boolean = true, 148 RenameSnapshotNum: Int = 4, 149 FtqSize: Int = 64, 150 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 151 IntLogicRegs: Int = 32, 152 FpLogicRegs: Int = 33, 153 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 154 VCONFIG_IDX: Int = 32, 155 NRPhyRegs: Int = 192, 156 VirtualLoadQueueSize: Int = 80, 157 LoadQueueRARSize: Int = 80, 158 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 159 RollbackGroupSize: Int = 8, 160 LoadQueueReplaySize: Int = 72, 161 LoadUncacheBufferSize: Int = 20, 162 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 163 StoreQueueSize: Int = 64, 164 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 165 StoreQueueForwardWithMask: Boolean = true, 166 VlsQueueSize: Int = 8, 167 RobSize: Int = 256, 168 RabSize: Int = 256, 169 IssueQueueSize: Int = 32, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 16, 174 IntDqDeqWidth = 6, 175 FpDqDeqWidth = 6, 176 LsDqDeqWidth = 6, 177 ), 178 intPreg: PregParams = IntPregParams( 179 numEntries = 192, 180 numRead = None, 181 numWrite = None, 182 ), 183 vfPreg: VfPregParams = VfPregParams( 184 numEntries = 192, 185 numRead = None, 186 numWrite = None, 187 ), 188 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 189 LoadPipelineWidth: Int = 2, 190 StorePipelineWidth: Int = 2, 191 VecMemSrcInWidth: Int = 2, 192 VecMemInstWbWidth: Int = 1, 193 VecMemDispatchWidth: Int = 1, 194 StoreBufferSize: Int = 16, 195 StoreBufferThreshold: Int = 7, 196 EnsbufferWidth: Int = 2, 197 UncacheBufferSize: Int = 4, 198 EnableLoadToLoadForward: Boolean = true, 199 EnableFastForward: Boolean = true, 200 EnableLdVioCheckAfterReset: Boolean = true, 201 EnableSoftPrefetchAfterReset: Boolean = true, 202 EnableCacheErrorAfterReset: Boolean = true, 203 EnableAccurateLoadError: Boolean = true, 204 EnableUncacheWriteOutstanding: Boolean = false, 205 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 206 ReSelectLen: Int = 7, // load replay queue replay select counter len 207 iwpuParameters: WPUParameters = WPUParameters( 208 enWPU = false, 209 algoName = "mmru", 210 isICache = true, 211 ), 212 dwpuParameters: WPUParameters = WPUParameters( 213 enWPU = false, 214 algoName = "mmru", 215 enCfPred = false, 216 isICache = false, 217 ), 218 itlbParameters: TLBParameters = TLBParameters( 219 name = "itlb", 220 fetchi = true, 221 useDmode = false, 222 normalNWays = 32, 223 normalReplacer = Some("plru"), 224 superNWays = 4, 225 superReplacer = Some("plru") 226 ), 227 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 228 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 229 ldtlbParameters: TLBParameters = TLBParameters( 230 name = "ldtlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 sttlbParameters: TLBParameters = TLBParameters( 243 name = "sttlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 pftlbParameters: TLBParameters = TLBParameters( 256 name = "pftlb", 257 normalNSets = 64, 258 normalNWays = 1, 259 normalAssociative = "sa", 260 normalReplacer = Some("setplru"), 261 superNWays = 16, 262 normalAsVictim = true, 263 outReplace = false, 264 partialStaticPMP = true, 265 outsideRecvFlush = true, 266 saveLevel = true 267 ), 268 refillBothTlb: Boolean = false, 269 btlbParameters: TLBParameters = TLBParameters( 270 name = "btlb", 271 normalNSets = 1, 272 normalNWays = 64, 273 superNWays = 4, 274 ), 275 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 276 NumPerfCounters: Int = 16, 277 icacheParameters: ICacheParameters = ICacheParameters( 278 tagECC = Some("parity"), 279 dataECC = Some("parity"), 280 replacer = Some("setplru"), 281 nMissEntries = 2, 282 nProbeEntries = 2, 283 nPrefetchEntries = 12, 284 nPrefBufferEntries = 64, 285 hasPrefetch = true, 286 ), 287 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 288 tagECC = Some("secded"), 289 dataECC = Some("secded"), 290 replacer = Some("setplru"), 291 nMissEntries = 16, 292 nProbeEntries = 8, 293 nReleaseEntries = 18 294 )), 295 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 296 name = "l2", 297 ways = 8, 298 sets = 1024, // default 512KB L2 299 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 300 )), 301 L2NBanks: Int = 1, 302 usePTWRepeater: Boolean = false, 303 softTLB: Boolean = false, // dpi-c l1tlb debug only 304 softPTW: Boolean = false, // dpi-c l2tlb debug only 305 softPTWDelay: Int = 1 306){ 307 def vlWidth = log2Up(VLEN) + 1 308 309 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 310 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 311 312 val intSchdParams = { 313 implicit val schdType: SchedulerType = IntScheduler() 314 SchdBlockParams(Seq( 315 IssueBlockParams(Seq( 316 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 317 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 318 ), numEntries = 32, numEnq = 2), 319 IssueBlockParams(Seq( 320 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 321 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 322 ), numEntries = 32, numEnq = 2), 323 IssueBlockParams(Seq( 324 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 325 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 326 ), numEntries = 32, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 329 ), numEntries = 32, numEnq = 2), 330 IssueBlockParams(Seq( 331 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 332 ), numEntries = 32, numEnq = 2), 333 ), 334 numPregs = intPreg.numEntries, 335 numDeqOutside = 0, 336 schdType = schdType, 337 rfDataWidth = intPreg.dataCfg.dataWidth, 338 numUopIn = dpParams.IntDqDeqWidth, 339 ) 340 } 341 val vfSchdParams = { 342 implicit val schdType: SchedulerType = VfScheduler() 343 SchdBlockParams(Seq( 344 IssueBlockParams(Seq( 345 ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))), 346 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))), 347 ), numEntries = 32, numEnq = 2), 348 IssueBlockParams(Seq( 349 ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))), 350 ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 3, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))), 351 ), numEntries = 32, numEnq = 2), 352 IssueBlockParams(Seq( 353 ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 354 ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 355 ), numEntries = 32, numEnq = 2), 356 IssueBlockParams(Seq( 357 ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 358 ), numEntries = 32, numEnq = 2), 359 ), 360 numPregs = vfPreg.numEntries, 361 numDeqOutside = 0, 362 schdType = schdType, 363 rfDataWidth = vfPreg.dataCfg.dataWidth, 364 numUopIn = dpParams.FpDqDeqWidth, 365 ) 366 } 367 368 val memSchdParams = { 369 implicit val schdType: SchedulerType = MemScheduler() 370 val rfDataWidth = 64 371 372 SchdBlockParams(Seq( 373 IssueBlockParams(Seq( 374 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 375 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 376 ), numEntries = 32, numEnq = 2), 377 IssueBlockParams(Seq( 378 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))), 379 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))), 380 ), numEntries = 32, numEnq = 2), 381 IssueBlockParams(Seq( 382 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 383 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 384 ), numEntries = 32, numEnq = 2), 385 IssueBlockParams(Seq( 386 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 387 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 388 ), numEntries = 32, numEnq = 2), 389 ), 390 numPregs = intPreg.numEntries max vfPreg.numEntries, 391 numDeqOutside = 0, 392 schdType = schdType, 393 rfDataWidth = rfDataWidth, 394 numUopIn = dpParams.LsDqDeqWidth, 395 ) 396 } 397 398 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 399 400 def iqWakeUpParams = { 401 Seq( 402 WakeUpConfig("ALU0" -> "ALU0"), 403 WakeUpConfig("ALU0" -> "ALU1"), 404 WakeUpConfig("ALU0" -> "MUL0"), 405 WakeUpConfig("ALU0" -> "MUL1"), 406 WakeUpConfig("ALU1" -> "ALU0"), 407 WakeUpConfig("ALU1" -> "ALU1"), 408 WakeUpConfig("ALU0" -> "BJU0"), 409 WakeUpConfig("ALU0" -> "BJU1"), 410 WakeUpConfig("ALU1" -> "BJU0"), 411 WakeUpConfig("ALU1" -> "BJU1"), 412 WakeUpConfig("ALU0" -> "LDU0"), 413 WakeUpConfig("ALU0" -> "LDU1"), 414 WakeUpConfig("ALU1" -> "LDU0"), 415 WakeUpConfig("ALU1" -> "LDU1"), 416 WakeUpConfig("ALU0" -> "STA0"), 417 WakeUpConfig("ALU0" -> "STA1"), 418 WakeUpConfig("ALU1" -> "STA0"), 419 WakeUpConfig("ALU1" -> "STA1"), 420 WakeUpConfig("MUL0" -> "ALU0"), 421 WakeUpConfig("MUL0" -> "ALU1"), 422 WakeUpConfig("MUL0" -> "MUL0"), 423 WakeUpConfig("MUL0" -> "MUL1"), 424 WakeUpConfig("MUL1" -> "ALU0"), 425 WakeUpConfig("MUL1" -> "ALU1"), 426 WakeUpConfig("MUL0" -> "BJU0"), 427 WakeUpConfig("MUL0" -> "BJU1"), 428 WakeUpConfig("MUL1" -> "BJU0"), 429 WakeUpConfig("MUL1" -> "BJU1"), 430 WakeUpConfig("MUL0" -> "LDU0"), 431 WakeUpConfig("MUL0" -> "LDU1"), 432 WakeUpConfig("MUL1" -> "LDU0"), 433 WakeUpConfig("MUL1" -> "LDU1"), 434 WakeUpConfig("MUL0" -> "STA0"), 435 WakeUpConfig("MUL0" -> "STA1"), 436 WakeUpConfig("MUL1" -> "STA0"), 437 WakeUpConfig("MUL1" -> "STA1"), 438 WakeUpConfig("IMISC0" -> "FEX0"), 439 WakeUpConfig("IMISC0" -> "FEX1"), 440 WakeUpConfig("IMISC0" -> "FEX2"), 441 WakeUpConfig("IMISC0" -> "FEX3"), 442 WakeUpConfig("IMISC0" -> "FEX4"), 443 WakeUpConfig("FEX3" -> "FEX0"), 444 WakeUpConfig("FEX3" -> "FEX1"), 445 WakeUpConfig("FEX3" -> "FEX2"), 446 WakeUpConfig("FEX3" -> "FEX3"), 447 ) 448 } 449 450 def backendParams: BackendParams = backend.BackendParams( 451 Map( 452 IntScheduler() -> intSchdParams, 453 VfScheduler() -> vfSchdParams, 454 MemScheduler() -> memSchdParams, 455 ), 456 Seq( 457 intPreg, 458 vfPreg, 459 ), 460 iqWakeUpParams, 461 ) 462} 463 464case object DebugOptionsKey extends Field[DebugOptions] 465 466case class DebugOptions 467( 468 FPGAPlatform: Boolean = false, 469 EnableDifftest: Boolean = false, 470 AlwaysBasicDiff: Boolean = true, 471 EnableDebug: Boolean = false, 472 EnablePerfDebug: Boolean = true, 473 UseDRAMSim: Boolean = false, 474 EnableConstantin: Boolean = false, 475 EnableChiselDB: Boolean = false, 476 AlwaysBasicDB: Boolean = true, 477 EnableTopDown: Boolean = false, 478) 479 480trait HasXSParameter { 481 482 implicit val p: Parameters 483 484 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 485 486 val coreParams = p(XSCoreParamsKey) 487 val env = p(DebugOptionsKey) 488 489 val XLEN = coreParams.XLEN 490 val VLEN = coreParams.VLEN 491 val ELEN = coreParams.ELEN 492 val minFLen = 32 493 val fLen = 64 494 def xLen = XLEN 495 496 val HasMExtension = coreParams.HasMExtension 497 val HasCExtension = coreParams.HasCExtension 498 val HasDiv = coreParams.HasDiv 499 val HasIcache = coreParams.HasICache 500 val HasDcache = coreParams.HasDCache 501 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 502 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 503 val AsidLength = coreParams.AsidLength 504 val ReSelectLen = coreParams.ReSelectLen 505 val AddrBytes = AddrBits / 8 // unused 506 val DataBits = XLEN 507 val DataBytes = DataBits / 8 508 val VDataBytes = VLEN / 8 509 val HasFPU = coreParams.HasFPU 510 val HasVPU = coreParams.HasVPU 511 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 512 val FetchWidth = coreParams.FetchWidth 513 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 514 val EnableBPU = coreParams.EnableBPU 515 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 516 val EnableRAS = coreParams.EnableRAS 517 val EnableLB = coreParams.EnableLB 518 val EnableLoop = coreParams.EnableLoop 519 val EnableSC = coreParams.EnableSC 520 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 521 val HistoryLength = coreParams.HistoryLength 522 val EnableGHistDiff = coreParams.EnableGHistDiff 523 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 524 val UbtbGHRLength = coreParams.UbtbGHRLength 525 val UbtbSize = coreParams.UbtbSize 526 val EnableFauFTB = coreParams.EnableFauFTB 527 val FtbSize = coreParams.FtbSize 528 val FtbWays = coreParams.FtbWays 529 val RasSize = coreParams.RasSize 530 531 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 532 coreParams.branchPredictor(resp_in, p) 533 } 534 val numBr = coreParams.numBr 535 val TageTableInfos = coreParams.TageTableInfos 536 val TageBanks = coreParams.numBr 537 val SCNRows = coreParams.SCNRows 538 val SCCtrBits = coreParams.SCCtrBits 539 val SCHistLens = coreParams.SCHistLens 540 val SCNTables = coreParams.SCNTables 541 542 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 543 case ((n, cb), h) => (n, cb, h) 544 } 545 val ITTageTableInfos = coreParams.ITTageTableInfos 546 type FoldedHistoryInfo = Tuple2[Int, Int] 547 val foldedGHistInfos = 548 (TageTableInfos.map{ case (nRows, h, t) => 549 if (h > 0) 550 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 551 else 552 Set[FoldedHistoryInfo]() 553 }.reduce(_++_).toSet ++ 554 SCTableInfos.map{ case (nRows, _, h) => 555 if (h > 0) 556 Set((h, min(log2Ceil(nRows/TageBanks), h))) 557 else 558 Set[FoldedHistoryInfo]() 559 }.reduce(_++_).toSet ++ 560 ITTageTableInfos.map{ case (nRows, h, t) => 561 if (h > 0) 562 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 563 else 564 Set[FoldedHistoryInfo]() 565 }.reduce(_++_) ++ 566 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 567 ).toList 568 569 570 571 val CacheLineSize = coreParams.CacheLineSize 572 val CacheLineHalfWord = CacheLineSize / 16 573 val ExtHistoryLength = HistoryLength + 64 574 val IBufSize = coreParams.IBufSize 575 val DecodeWidth = coreParams.DecodeWidth 576 val RenameWidth = coreParams.RenameWidth 577 val CommitWidth = coreParams.CommitWidth 578 val MaxUopSize = coreParams.MaxUopSize 579 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 580 val RenameSnapshotNum = coreParams.RenameSnapshotNum 581 val FtqSize = coreParams.FtqSize 582 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 583 val IntLogicRegs = coreParams.IntLogicRegs 584 val FpLogicRegs = coreParams.FpLogicRegs 585 val VecLogicRegs = coreParams.VecLogicRegs 586 val VCONFIG_IDX = coreParams.VCONFIG_IDX 587 val IntPhyRegs = coreParams.intPreg.numEntries 588 val VfPhyRegs = coreParams.vfPreg.numEntries 589 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 590 val RobSize = coreParams.RobSize 591 val RabSize = coreParams.RabSize 592 val IntRefCounterWidth = log2Ceil(RobSize) 593 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 594 val LoadQueueRARSize = coreParams.LoadQueueRARSize 595 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 596 val RollbackGroupSize = coreParams.RollbackGroupSize 597 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 598 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 599 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 600 val StoreQueueSize = coreParams.StoreQueueSize 601 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 602 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 603 val VlsQueueSize = coreParams.VlsQueueSize 604 val dpParams = coreParams.dpParams 605 606 def backendParams: BackendParams = coreParams.backendParams 607 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 608 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 609 val LoadPipelineWidth = coreParams.LoadPipelineWidth 610 val StorePipelineWidth = coreParams.StorePipelineWidth 611 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 612 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 613 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 614 val StoreBufferSize = coreParams.StoreBufferSize 615 val StoreBufferThreshold = coreParams.StoreBufferThreshold 616 val EnsbufferWidth = coreParams.EnsbufferWidth 617 val UncacheBufferSize = coreParams.UncacheBufferSize 618 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 619 val EnableFastForward = coreParams.EnableFastForward 620 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 621 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 622 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 623 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 624 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 625 val asidLen = coreParams.MMUAsidLen 626 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 627 val refillBothTlb = coreParams.refillBothTlb 628 val iwpuParam = coreParams.iwpuParameters 629 val dwpuParam = coreParams.dwpuParameters 630 val itlbParams = coreParams.itlbParameters 631 val ldtlbParams = coreParams.ldtlbParameters 632 val sttlbParams = coreParams.sttlbParameters 633 val pftlbParams = coreParams.pftlbParameters 634 val btlbParams = coreParams.btlbParameters 635 val l2tlbParams = coreParams.l2tlbParameters 636 val NumPerfCounters = coreParams.NumPerfCounters 637 638 val instBytes = if (HasCExtension) 2 else 4 639 val instOffsetBits = log2Ceil(instBytes) 640 641 val icacheParameters = coreParams.icacheParameters 642 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 643 644 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 645 // for constrained LR/SC loop 646 val LRSCCycles = 64 647 // for lr storm 648 val LRSCBackOff = 8 649 650 // cache hierarchy configurations 651 val l1BusDataWidth = 256 652 653 // load violation predict 654 val ResetTimeMax2Pow = 20 //1078576 655 val ResetTimeMin2Pow = 10 //1024 656 // wait table parameters 657 val WaitTableSize = 1024 658 val MemPredPCWidth = log2Up(WaitTableSize) 659 val LWTUse2BitCounter = true 660 // store set parameters 661 val SSITSize = WaitTableSize 662 val LFSTSize = 32 663 val SSIDWidth = log2Up(LFSTSize) 664 val LFSTWidth = 4 665 val StoreSetEnable = true // LWT will be disabled if SS is enabled 666 val LFSTEnable = false 667 668 val PCntIncrStep: Int = 6 669 val numPCntHc: Int = 25 670 val numPCntPtw: Int = 19 671 672 val numCSRPCntFrontend = 8 673 val numCSRPCntCtrl = 8 674 val numCSRPCntLsu = 8 675 val numCSRPCntHc = 5 676} 677