1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31 32case object XSTileKey extends Field[Seq[XSCoreParameters]] 33 34case object XSCoreParamsKey extends Field[XSCoreParameters] 35 36case class XSCoreParameters 37( 38 HasPrefetch: Boolean = false, 39 HartId: Int = 0, 40 XLEN: Int = 64, 41 HasMExtension: Boolean = true, 42 HasCExtension: Boolean = true, 43 HasDiv: Boolean = true, 44 HasICache: Boolean = true, 45 HasDCache: Boolean = true, 46 AddrBits: Int = 64, 47 VAddrBits: Int = 39, 48 HasFPU: Boolean = true, 49 HasCustomCSRCacheOp: Boolean = true, 50 FetchWidth: Int = 8, 51 AsidLength: Int = 16, 52 EnableBPU: Boolean = true, 53 EnableBPD: Boolean = true, 54 EnableRAS: Boolean = true, 55 EnableLB: Boolean = false, 56 EnableLoop: Boolean = true, 57 EnableSC: Boolean = true, 58 EnbaleTlbDebug: Boolean = false, 59 EnableJal: Boolean = false, 60 EnableUBTB: Boolean = true, 61 HistoryLength: Int = 64, 62 PathHistoryLength: Int = 16, 63 BtbSize: Int = 2048, 64 JbtacSize: Int = 1024, 65 JbtacBanks: Int = 8, 66 RasSize: Int = 32, 67 CacheLineSize: Int = 512, 68 UBtbWays: Int = 16, 69 BtbWays: Int = 2, 70 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 71 ((resp_in: BranchPredictionResp, p: Parameters) => { 72 // val loop = Module(new LoopPredictor) 73 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 74 // else Module(new Tage) } 75 // else { Module(new FakeTage) }) 76 val ftb = Module(new FTB()(p)) 77 val ubtb = Module(new MicroBTB()(p)) 78 val bim = Module(new BIM()(p)) 79 val tage = Module(new Tage_SC()(p)) 80 val ras = Module(new RAS()(p)) 81 val ittage = Module(new ITTage()(p)) 82 // val tage = Module(new Tage()(p)) 83 // val fake = Module(new FakePredictor()(p)) 84 85 // val preds = Seq(loop, tage, btb, ubtb, bim) 86 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 87 preds.map(_.io := DontCare) 88 89 // ubtb.io.resp_in(0) := resp_in 90 // bim.io.resp_in(0) := ubtb.io.resp 91 // btb.io.resp_in(0) := bim.io.resp 92 // tage.io.resp_in(0) := btb.io.resp 93 // loop.io.resp_in(0) := tage.io.resp 94 bim.io.in.bits.resp_in(0) := resp_in 95 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 96 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 97 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 98 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 99 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 100 101 (preds, ras.io.out.resp) 102 }), 103 IBufSize: Int = 48, 104 DecodeWidth: Int = 6, 105 RenameWidth: Int = 6, 106 CommitWidth: Int = 6, 107 FtqSize: Int = 64, 108 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 109 IssQueSize: Int = 16, 110 NRPhyRegs: Int = 192, 111 NRIntReadPorts: Int = 14, 112 NRIntWritePorts: Int = 8, 113 NRFpReadPorts: Int = 14, 114 NRFpWritePorts: Int = 8, 115 LoadQueueSize: Int = 80, 116 StoreQueueSize: Int = 64, 117 RobSize: Int = 256, 118 dpParams: DispatchParameters = DispatchParameters( 119 IntDqSize = 16, 120 FpDqSize = 16, 121 LsDqSize = 16, 122 IntDqDeqWidth = 4, 123 FpDqDeqWidth = 4, 124 LsDqDeqWidth = 4 125 ), 126 exuParameters: ExuParameters = ExuParameters( 127 JmpCnt = 1, 128 AluCnt = 4, 129 MulCnt = 0, 130 MduCnt = 2, 131 FmacCnt = 4, 132 FmiscCnt = 2, 133 FmiscDivSqrtCnt = 0, 134 LduCnt = 2, 135 StuCnt = 2 136 ), 137 LoadPipelineWidth: Int = 2, 138 StorePipelineWidth: Int = 2, 139 StoreBufferSize: Int = 16, 140 StoreBufferThreshold: Int = 7, 141 EnableFastForward: Boolean = true, 142 EnableLdVioCheckAfterReset: Boolean = true, 143 RefillSize: Int = 512, 144 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 145 itlbParameters: TLBParameters = TLBParameters( 146 name = "itlb", 147 fetchi = true, 148 useDmode = false, 149 sameCycle = true, 150 normalNWays = 32, 151 normalReplacer = Some("plru"), 152 superNWays = 4, 153 superReplacer = Some("plru"), 154 shouldBlock = true 155 ), 156 ldtlbParameters: TLBParameters = TLBParameters( 157 name = "ldtlb", 158 normalNSets = 128, 159 normalNWays = 1, 160 normalAssociative = "sa", 161 normalReplacer = Some("setplru"), 162 superNWays = 8, 163 normalAsVictim = true, 164 outReplace = true, 165 saveLevel = true 166 ), 167 sttlbParameters: TLBParameters = TLBParameters( 168 name = "sttlb", 169 normalNSets = 128, 170 normalNWays = 1, 171 normalAssociative = "sa", 172 normalReplacer = Some("setplru"), 173 superNWays = 8, 174 normalAsVictim = true, 175 outReplace = true, 176 saveLevel = true 177 ), 178 refillBothTlb: Boolean = false, 179 btlbParameters: TLBParameters = TLBParameters( 180 name = "btlb", 181 normalNSets = 1, 182 normalNWays = 64, 183 superNWays = 4, 184 ), 185 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 186 NumPMP: Int = 16, // 0 or 16 or 64 187 NumPMA: Int = 16, 188 NumPerfCounters: Int = 16, 189 icacheParameters: ICacheParameters = ICacheParameters( 190 tagECC = Some("parity"), 191 dataECC = Some("parity"), 192 replacer = Some("setplru"), 193 nMissEntries = 2 194 ), 195 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 196 tagECC = Some("secded"), 197 dataECC = Some("secded"), 198 replacer = Some("setplru"), 199 nMissEntries = 16, 200 nProbeEntries = 8, 201 nReleaseEntries = 18 202 )), 203 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 204 name = "l2", 205 level = 2, 206 ways = 8, 207 sets = 1024, // default 512KB L2 208 prefetch = Some(huancun.prefetch.BOPParameters()) 209 )), 210 L2NBanks: Int = 1, 211 usePTWRepeater: Boolean = false, 212 softPTW: Boolean = false // dpi-c debug only 213){ 214 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 215 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 216 217 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 218 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 219 220 val fpExuConfigs = 221 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 222 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 223 224 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 225} 226 227case object DebugOptionsKey extends Field[DebugOptions] 228 229case class DebugOptions 230( 231 FPGAPlatform: Boolean = false, 232 EnableDifftest: Boolean = false, 233 EnableDebug: Boolean = false, 234 EnablePerfDebug: Boolean = true, 235 UseDRAMSim: Boolean = false 236) 237 238trait HasXSParameter { 239 240 implicit val p: Parameters 241 242 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 243 244 val coreParams = p(XSCoreParamsKey) 245 val env = p(DebugOptionsKey) 246 247 val XLEN = coreParams.XLEN 248 val hardId = coreParams.HartId 249 val minFLen = 32 250 val fLen = 64 251 def xLen = XLEN 252 253 val HasMExtension = coreParams.HasMExtension 254 val HasCExtension = coreParams.HasCExtension 255 val HasDiv = coreParams.HasDiv 256 val HasIcache = coreParams.HasICache 257 val HasDcache = coreParams.HasDCache 258 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 259 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 260 val AsidLength = coreParams.AsidLength 261 val AddrBytes = AddrBits / 8 // unused 262 val DataBits = XLEN 263 val DataBytes = DataBits / 8 264 val HasFPU = coreParams.HasFPU 265 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 266 val FetchWidth = coreParams.FetchWidth 267 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 268 val EnableBPU = coreParams.EnableBPU 269 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 270 val EnableRAS = coreParams.EnableRAS 271 val EnableLB = coreParams.EnableLB 272 val EnableLoop = coreParams.EnableLoop 273 val EnableSC = coreParams.EnableSC 274 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 275 val HistoryLength = coreParams.HistoryLength 276 val PathHistoryLength = coreParams.PathHistoryLength 277 val BtbSize = coreParams.BtbSize 278 // val BtbWays = 4 279 val BtbBanks = PredictWidth 280 // val BtbSets = BtbSize / BtbWays 281 val JbtacSize = coreParams.JbtacSize 282 val JbtacBanks = coreParams.JbtacBanks 283 val RasSize = coreParams.RasSize 284 285 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 286 coreParams.branchPredictor(resp_in, p) 287 } 288 289 val CacheLineSize = coreParams.CacheLineSize 290 val CacheLineHalfWord = CacheLineSize / 16 291 val ExtHistoryLength = HistoryLength + 64 292 val UBtbWays = coreParams.UBtbWays 293 val BtbWays = coreParams.BtbWays 294 val IBufSize = coreParams.IBufSize 295 val DecodeWidth = coreParams.DecodeWidth 296 val RenameWidth = coreParams.RenameWidth 297 val CommitWidth = coreParams.CommitWidth 298 val FtqSize = coreParams.FtqSize 299 val IssQueSize = coreParams.IssQueSize 300 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 301 val NRPhyRegs = coreParams.NRPhyRegs 302 val PhyRegIdxWidth = log2Up(NRPhyRegs) 303 val RobSize = coreParams.RobSize 304 val IntRefCounterWidth = log2Ceil(RobSize) 305 val StdFreeListSize = NRPhyRegs - 32 306 val MEFreeListSize = NRPhyRegs 307 val LoadQueueSize = coreParams.LoadQueueSize 308 val StoreQueueSize = coreParams.StoreQueueSize 309 val dpParams = coreParams.dpParams 310 val exuParameters = coreParams.exuParameters 311 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 312 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 313 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 314 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 315 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 316 val LoadPipelineWidth = coreParams.LoadPipelineWidth 317 val StorePipelineWidth = coreParams.StorePipelineWidth 318 val StoreBufferSize = coreParams.StoreBufferSize 319 val StoreBufferThreshold = coreParams.StoreBufferThreshold 320 val EnableFastForward = coreParams.EnableFastForward 321 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 322 val RefillSize = coreParams.RefillSize 323 val asidLen = coreParams.MMUAsidLen 324 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 325 val refillBothTlb = coreParams.refillBothTlb 326 val itlbParams = coreParams.itlbParameters 327 val ldtlbParams = coreParams.ldtlbParameters 328 val sttlbParams = coreParams.sttlbParameters 329 val btlbParams = coreParams.btlbParameters 330 val l2tlbParams = coreParams.l2tlbParameters 331 val NumPMP = coreParams.NumPMP 332 val NumPMA = coreParams.NumPMA 333 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 334 val NumPerfCounters = coreParams.NumPerfCounters 335 336 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 337 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 338 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 339 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 340 341 val instBytes = if (HasCExtension) 2 else 4 342 val instOffsetBits = log2Ceil(instBytes) 343 344 val icacheParameters = coreParams.icacheParameters 345 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 346 347 val LRSCCycles = 100 348 349 // cache hierarchy configurations 350 val l1BusDataWidth = 256 351 352 // load violation predict 353 val ResetTimeMax2Pow = 20 //1078576 354 val ResetTimeMin2Pow = 10 //1024 355 // wait table parameters 356 val WaitTableSize = 1024 357 val MemPredPCWidth = log2Up(WaitTableSize) 358 val LWTUse2BitCounter = true 359 // store set parameters 360 val SSITSize = WaitTableSize 361 val LFSTSize = 32 362 val SSIDWidth = log2Up(LFSTSize) 363 val LFSTWidth = 4 364 val StoreSetEnable = true // LWT will be disabled if SS is enabled 365 366 val loadExuConfigs = coreParams.loadExuConfigs 367 val storeExuConfigs = coreParams.storeExuConfigs 368 369 val intExuConfigs = coreParams.intExuConfigs 370 371 val fpExuConfigs = coreParams.fpExuConfigs 372 373 val exuConfigs = coreParams.exuConfigs 374 375 val PCntIncrStep: Int = 6 376 val numPCntHc: Int = 25 377 val numPCntPtw: Int = 19 378 379 val numCSRPCntFrontend = 8 380 val numCSRPCntCtrl = 8 381 val numCSRPCntLsu = 8 382 val numCSRPCntHc = 5 383 val print_perfcounter = false 384} 385