1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 PathHistoryLength: Int = 16, 66 BtbSize: Int = 2048, 67 JbtacSize: Int = 1024, 68 JbtacBanks: Int = 8, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 UBtbWays: Int = 16, 72 BtbWays: Int = 2, 73 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 74 // Sets Hist Tag 75 Seq(( 128*8, 2, 7), 76 ( 128*8, 4, 7), 77 ( 256*8, 8, 8), 78 ( 256*8, 16, 8), 79 ( 128*8, 32, 9), 80 ( 128*8, 65, 9)), 81 TageBanks: Int = 2, 82 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 83 // Sets Hist Tag 84 Seq(( 512, 0, 0), 85 ( 256, 4, 8), 86 ( 256, 8, 8), 87 ( 512, 12, 8), 88 ( 512, 16, 8), 89 ( 512, 32, 8)), 90 SCNRows: Int = 1024, 91 SCNTables: Int = 6, 92 SCCtrBits: Int = 6, 93 numBr: Int = 2, 94 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 95 ((resp_in: BranchPredictionResp, p: Parameters) => { 96 // val loop = Module(new LoopPredictor) 97 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 98 // else Module(new Tage) } 99 // else { Module(new FakeTage) }) 100 val ftb = Module(new FTB()(p)) 101 val ubtb = Module(new MicroBTB()(p)) 102 val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 // val tage = Module(new Tage()(p)) 107 // val fake = Module(new FakePredictor()(p)) 108 109 // val preds = Seq(loop, tage, btb, ubtb, bim) 110 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 bim.io.in.bits.resp_in(0) := resp_in 119 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 120 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 121 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 122 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 123 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 124 125 (preds, ras.io.out.resp) 126 }), 127 IBufSize: Int = 48, 128 DecodeWidth: Int = 6, 129 RenameWidth: Int = 6, 130 CommitWidth: Int = 6, 131 FtqSize: Int = 64, 132 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 133 IssQueSize: Int = 16, 134 NRPhyRegs: Int = 192, 135 LoadQueueSize: Int = 80, 136 StoreQueueSize: Int = 64, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 LoadPipelineWidth: Int = 2, 158 StorePipelineWidth: Int = 2, 159 StoreBufferSize: Int = 16, 160 StoreBufferThreshold: Int = 7, 161 EnableLoadToLoadForward: Boolean = false, 162 EnableFastForward: Boolean = false, 163 EnableLdVioCheckAfterReset: Boolean = true, 164 RefillSize: Int = 512, 165 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 166 itlbParameters: TLBParameters = TLBParameters( 167 name = "itlb", 168 fetchi = true, 169 useDmode = false, 170 sameCycle = false, 171 missSameCycle = true, 172 normalNWays = 32, 173 normalReplacer = Some("plru"), 174 superNWays = 4, 175 superReplacer = Some("plru"), 176 shouldBlock = true 177 ), 178 ldtlbParameters: TLBParameters = TLBParameters( 179 name = "ldtlb", 180 normalNSets = 128, 181 normalNWays = 1, 182 normalAssociative = "sa", 183 normalReplacer = Some("setplru"), 184 superNWays = 8, 185 normalAsVictim = true, 186 outReplace = true, 187 partialStaticPMP = true, 188 saveLevel = true 189 ), 190 sttlbParameters: TLBParameters = TLBParameters( 191 name = "sttlb", 192 normalNSets = 128, 193 normalNWays = 1, 194 normalAssociative = "sa", 195 normalReplacer = Some("setplru"), 196 superNWays = 8, 197 normalAsVictim = true, 198 outReplace = true, 199 partialStaticPMP = true, 200 saveLevel = true 201 ), 202 refillBothTlb: Boolean = false, 203 btlbParameters: TLBParameters = TLBParameters( 204 name = "btlb", 205 normalNSets = 1, 206 normalNWays = 64, 207 superNWays = 4, 208 ), 209 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 210 NumPerfCounters: Int = 16, 211 icacheParameters: ICacheParameters = ICacheParameters( 212 tagECC = Some("parity"), 213 dataECC = Some("parity"), 214 replacer = Some("setplru"), 215 nMissEntries = 2, 216 nReleaseEntries = 2 217 ), 218 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 219 tagECC = Some("secded"), 220 dataECC = Some("secded"), 221 replacer = Some("setplru"), 222 nMissEntries = 16, 223 nProbeEntries = 8, 224 nReleaseEntries = 18 225 )), 226 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 227 name = "l2", 228 level = 2, 229 ways = 8, 230 sets = 1024, // default 512KB L2 231 prefetch = Some(huancun.prefetch.BOPParameters()) 232 )), 233 L2NBanks: Int = 1, 234 usePTWRepeater: Boolean = false, 235 softPTW: Boolean = false // dpi-c debug only 236){ 237 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 238 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 239 240 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 241 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 242 243 val fpExuConfigs = 244 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 245 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 246 247 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 248} 249 250case object DebugOptionsKey extends Field[DebugOptions] 251 252case class DebugOptions 253( 254 FPGAPlatform: Boolean = false, 255 EnableDifftest: Boolean = false, 256 AlwaysBasicDiff: Boolean = true, 257 EnableDebug: Boolean = false, 258 EnablePerfDebug: Boolean = true, 259 UseDRAMSim: Boolean = false 260) 261 262trait HasXSParameter { 263 264 implicit val p: Parameters 265 266 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 267 268 val coreParams = p(XSCoreParamsKey) 269 val env = p(DebugOptionsKey) 270 271 val XLEN = coreParams.XLEN 272 val minFLen = 32 273 val fLen = 64 274 def xLen = XLEN 275 276 val HasMExtension = coreParams.HasMExtension 277 val HasCExtension = coreParams.HasCExtension 278 val HasDiv = coreParams.HasDiv 279 val HasIcache = coreParams.HasICache 280 val HasDcache = coreParams.HasDCache 281 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 282 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 283 val AsidLength = coreParams.AsidLength 284 val AddrBytes = AddrBits / 8 // unused 285 val DataBits = XLEN 286 val DataBytes = DataBits / 8 287 val HasFPU = coreParams.HasFPU 288 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 289 val FetchWidth = coreParams.FetchWidth 290 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 291 val EnableBPU = coreParams.EnableBPU 292 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 293 val EnableRAS = coreParams.EnableRAS 294 val EnableLB = coreParams.EnableLB 295 val EnableLoop = coreParams.EnableLoop 296 val EnableSC = coreParams.EnableSC 297 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 298 val HistoryLength = coreParams.HistoryLength 299 val PathHistoryLength = coreParams.PathHistoryLength 300 val BtbSize = coreParams.BtbSize 301 // val BtbWays = 4 302 val BtbBanks = PredictWidth 303 // val BtbSets = BtbSize / BtbWays 304 val JbtacSize = coreParams.JbtacSize 305 val JbtacBanks = coreParams.JbtacBanks 306 val RasSize = coreParams.RasSize 307 308 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 309 coreParams.branchPredictor(resp_in, p) 310 } 311 val numBr = coreParams.numBr 312 val TageTableInfos = coreParams.TageTableInfos 313 314 315 val BankTageTableInfos = (0 until numBr).map(i => 316 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 317 ) 318 val TageBanks = coreParams.TageBanks 319 val SCNRows = coreParams.SCNRows 320 val SCCtrBits = coreParams.SCCtrBits 321 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 322 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 323 324 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 325 case (ntable, histlens) => 326 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 327 } 328 val ITTageTableInfos = coreParams.ITTageTableInfos 329 type FoldedHistoryInfo = Tuple2[Int, Int] 330 val foldedGHistInfos = 331 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 332 if (h > 0) 333 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 334 else 335 Set[FoldedHistoryInfo]() 336 }.reduce(_++_)).toSet ++ 337 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 338 if (h > 0) 339 Set((h, min(log2Ceil(nRows/TageBanks), h))) 340 else 341 Set[FoldedHistoryInfo]() 342 }.reduce(_++_)).toSet ++ 343 ITTageTableInfos.map{ case (nRows, h, t) => 344 if (h > 0) 345 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 346 else 347 Set[FoldedHistoryInfo]() 348 }.reduce(_++_)).toList 349 350 val CacheLineSize = coreParams.CacheLineSize 351 val CacheLineHalfWord = CacheLineSize / 16 352 val ExtHistoryLength = HistoryLength + 64 353 val UBtbWays = coreParams.UBtbWays 354 val BtbWays = coreParams.BtbWays 355 val IBufSize = coreParams.IBufSize 356 val DecodeWidth = coreParams.DecodeWidth 357 val RenameWidth = coreParams.RenameWidth 358 val CommitWidth = coreParams.CommitWidth 359 val FtqSize = coreParams.FtqSize 360 val IssQueSize = coreParams.IssQueSize 361 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 362 val NRPhyRegs = coreParams.NRPhyRegs 363 val PhyRegIdxWidth = log2Up(NRPhyRegs) 364 val RobSize = coreParams.RobSize 365 val IntRefCounterWidth = log2Ceil(RobSize) 366 val LoadQueueSize = coreParams.LoadQueueSize 367 val StoreQueueSize = coreParams.StoreQueueSize 368 val dpParams = coreParams.dpParams 369 val exuParameters = coreParams.exuParameters 370 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 371 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 372 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 373 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 374 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 375 val LoadPipelineWidth = coreParams.LoadPipelineWidth 376 val StorePipelineWidth = coreParams.StorePipelineWidth 377 val StoreBufferSize = coreParams.StoreBufferSize 378 val StoreBufferThreshold = coreParams.StoreBufferThreshold 379 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 380 val EnableFastForward = coreParams.EnableFastForward 381 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 382 val RefillSize = coreParams.RefillSize 383 val asidLen = coreParams.MMUAsidLen 384 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 385 val refillBothTlb = coreParams.refillBothTlb 386 val itlbParams = coreParams.itlbParameters 387 val ldtlbParams = coreParams.ldtlbParameters 388 val sttlbParams = coreParams.sttlbParameters 389 val btlbParams = coreParams.btlbParameters 390 val l2tlbParams = coreParams.l2tlbParameters 391 val NumPerfCounters = coreParams.NumPerfCounters 392 393 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 394 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 395 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 396 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 397 398 val instBytes = if (HasCExtension) 2 else 4 399 val instOffsetBits = log2Ceil(instBytes) 400 401 val icacheParameters = coreParams.icacheParameters 402 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 403 404 val LRSCCycles = 100 405 406 // cache hierarchy configurations 407 val l1BusDataWidth = 256 408 409 // load violation predict 410 val ResetTimeMax2Pow = 20 //1078576 411 val ResetTimeMin2Pow = 10 //1024 412 // wait table parameters 413 val WaitTableSize = 1024 414 val MemPredPCWidth = log2Up(WaitTableSize) 415 val LWTUse2BitCounter = true 416 // store set parameters 417 val SSITSize = WaitTableSize 418 val LFSTSize = 32 419 val SSIDWidth = log2Up(LFSTSize) 420 val LFSTWidth = 4 421 val StoreSetEnable = true // LWT will be disabled if SS is enabled 422 423 val loadExuConfigs = coreParams.loadExuConfigs 424 val storeExuConfigs = coreParams.storeExuConfigs 425 426 val intExuConfigs = coreParams.intExuConfigs 427 428 val fpExuConfigs = coreParams.fpExuConfigs 429 430 val exuConfigs = coreParams.exuConfigs 431 432 val PCntIncrStep: Int = 6 433 val numPCntHc: Int = 25 434 val numPCntPtw: Int = 19 435 436 val numCSRPCntFrontend = 8 437 val numCSRPCntCtrl = 8 438 val numCSRPCntLsu = 8 439 val numCSRPCntHc = 5 440} 441