1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 // HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = true, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 // Seq(( 2048, 2, 8), 75 // ( 2048, 9, 8), 76 // ( 2048, 13, 8), 77 // ( 2048, 20, 8), 78 // ( 2048, 26, 8), 79 // ( 2048, 44, 8), 80 // ( 2048, 73, 8), 81 // ( 2048, 256, 8)), 82 Seq(( 4096, 8, 8), 83 ( 4096, 13, 8), 84 ( 4096, 32, 8), 85 ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 // val loop = Module(new LoopPredictor) 101 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 102 // else Module(new Tage) } 103 // else { Module(new FakeTage) }) 104 val ftb = Module(new FTB()(p)) 105 val ubtb = Module(new MicroBTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 // val tage = Module(new Tage()(p)) 111 // val fake = Module(new FakePredictor()(p)) 112 113 // val preds = Seq(loop, tage, btb, ubtb, bim) 114 val preds = Seq(ubtb, tage, ftb, ittage, ras) 115 preds.map(_.io := DontCare) 116 117 // ubtb.io.resp_in(0) := resp_in 118 // bim.io.resp_in(0) := ubtb.io.resp 119 // btb.io.resp_in(0) := bim.io.resp 120 // tage.io.resp_in(0) := btb.io.resp 121 // loop.io.resp_in(0) := tage.io.resp 122 ubtb.io.in.bits.resp_in(0) := resp_in 123 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 124 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 125 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 126 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 127 128 (preds, ras.io.out.resp) 129 }), 130 IBufSize: Int = 48, 131 DecodeWidth: Int = 6, 132 RenameWidth: Int = 6, 133 CommitWidth: Int = 6, 134 FtqSize: Int = 64, 135 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 136 IssQueSize: Int = 16, 137 NRPhyRegs: Int = 192, 138 LoadQueueSize: Int = 80, 139 StoreQueueSize: Int = 64, 140 RobSize: Int = 256, 141 dpParams: DispatchParameters = DispatchParameters( 142 IntDqSize = 16, 143 FpDqSize = 16, 144 LsDqSize = 16, 145 IntDqDeqWidth = 4, 146 FpDqDeqWidth = 4, 147 LsDqDeqWidth = 4 148 ), 149 exuParameters: ExuParameters = ExuParameters( 150 JmpCnt = 1, 151 AluCnt = 4, 152 MulCnt = 0, 153 MduCnt = 2, 154 FmacCnt = 4, 155 FmiscCnt = 2, 156 FmiscDivSqrtCnt = 0, 157 LduCnt = 2, 158 StuCnt = 2 159 ), 160 LoadPipelineWidth: Int = 2, 161 StorePipelineWidth: Int = 2, 162 StoreBufferSize: Int = 16, 163 StoreBufferThreshold: Int = 7, 164 EnableLoadToLoadForward: Boolean = false, 165 EnableFastForward: Boolean = false, 166 EnableLdVioCheckAfterReset: Boolean = true, 167 EnableSoftPrefetchAfterReset: Boolean = true, 168 EnableCacheErrorAfterReset: Boolean = true, 169 RefillSize: Int = 512, 170 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 171 itlbParameters: TLBParameters = TLBParameters( 172 name = "itlb", 173 fetchi = true, 174 useDmode = false, 175 sameCycle = false, 176 missSameCycle = true, 177 normalNWays = 32, 178 normalReplacer = Some("plru"), 179 superNWays = 4, 180 superReplacer = Some("plru"), 181 shouldBlock = true 182 ), 183 ldtlbParameters: TLBParameters = TLBParameters( 184 name = "ldtlb", 185 normalNSets = 128, 186 normalNWays = 1, 187 normalAssociative = "sa", 188 normalReplacer = Some("setplru"), 189 superNWays = 8, 190 normalAsVictim = true, 191 outReplace = true, 192 partialStaticPMP = true, 193 saveLevel = true 194 ), 195 sttlbParameters: TLBParameters = TLBParameters( 196 name = "sttlb", 197 normalNSets = 128, 198 normalNWays = 1, 199 normalAssociative = "sa", 200 normalReplacer = Some("setplru"), 201 superNWays = 8, 202 normalAsVictim = true, 203 outReplace = true, 204 partialStaticPMP = true, 205 saveLevel = true 206 ), 207 refillBothTlb: Boolean = false, 208 btlbParameters: TLBParameters = TLBParameters( 209 name = "btlb", 210 normalNSets = 1, 211 normalNWays = 64, 212 superNWays = 4, 213 ), 214 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 215 NumPerfCounters: Int = 16, 216 icacheParameters: ICacheParameters = ICacheParameters( 217 tagECC = Some("parity"), 218 dataECC = Some("parity"), 219 replacer = Some("setplru"), 220 nMissEntries = 2, 221 nProbeEntries = 2, 222 nPrefetchEntries = 2, 223 hasPrefetch = true, 224 ), 225 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 226 tagECC = Some("secded"), 227 dataECC = Some("secded"), 228 replacer = Some("setplru"), 229 nMissEntries = 16, 230 nProbeEntries = 8, 231 nReleaseEntries = 18 232 )), 233 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 234 name = "l2", 235 level = 2, 236 ways = 8, 237 sets = 1024, // default 512KB L2 238 prefetch = Some(huancun.prefetch.BOPParameters()) 239 )), 240 L2NBanks: Int = 1, 241 usePTWRepeater: Boolean = false, 242 softPTW: Boolean = false // dpi-c debug only 243){ 244 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 245 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 246 247 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 248 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 249 250 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 251 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 252 253 val fpExuConfigs = 254 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 255 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 256 257 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 258} 259 260case object DebugOptionsKey extends Field[DebugOptions] 261 262case class DebugOptions 263( 264 FPGAPlatform: Boolean = false, 265 EnableDifftest: Boolean = false, 266 AlwaysBasicDiff: Boolean = true, 267 EnableDebug: Boolean = false, 268 EnablePerfDebug: Boolean = true, 269 UseDRAMSim: Boolean = false 270) 271 272trait HasXSParameter { 273 274 implicit val p: Parameters 275 276 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 277 278 val coreParams = p(XSCoreParamsKey) 279 val env = p(DebugOptionsKey) 280 281 val XLEN = coreParams.XLEN 282 val minFLen = 32 283 val fLen = 64 284 def xLen = XLEN 285 286 val HasMExtension = coreParams.HasMExtension 287 val HasCExtension = coreParams.HasCExtension 288 val HasDiv = coreParams.HasDiv 289 val HasIcache = coreParams.HasICache 290 val HasDcache = coreParams.HasDCache 291 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 292 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 293 val AsidLength = coreParams.AsidLength 294 val AddrBytes = AddrBits / 8 // unused 295 val DataBits = XLEN 296 val DataBytes = DataBits / 8 297 val HasFPU = coreParams.HasFPU 298 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 299 val FetchWidth = coreParams.FetchWidth 300 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 301 val EnableBPU = coreParams.EnableBPU 302 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 303 val EnableRAS = coreParams.EnableRAS 304 val EnableLB = coreParams.EnableLB 305 val EnableLoop = coreParams.EnableLoop 306 val EnableSC = coreParams.EnableSC 307 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 308 val HistoryLength = coreParams.HistoryLength 309 val EnableGHistDiff = coreParams.EnableGHistDiff 310 val UbtbGHRLength = coreParams.UbtbGHRLength 311 val UbtbSize = coreParams.UbtbSize 312 val FtbSize = coreParams.FtbSize 313 val FtbWays = coreParams.FtbWays 314 val RasSize = coreParams.RasSize 315 316 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 317 coreParams.branchPredictor(resp_in, p) 318 } 319 val numBr = coreParams.numBr 320 val TageTableInfos = coreParams.TageTableInfos 321 val TageBanks = coreParams.numBr 322 val SCNRows = coreParams.SCNRows 323 val SCCtrBits = coreParams.SCCtrBits 324 val SCHistLens = coreParams.SCHistLens 325 val SCNTables = coreParams.SCNTables 326 327 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 328 case ((n, cb), h) => (n, cb, h) 329 } 330 val ITTageTableInfos = coreParams.ITTageTableInfos 331 type FoldedHistoryInfo = Tuple2[Int, Int] 332 val foldedGHistInfos = 333 (TageTableInfos.map{ case (nRows, h, t) => 334 if (h > 0) 335 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 336 else 337 Set[FoldedHistoryInfo]() 338 }.reduce(_++_).toSet ++ 339 SCTableInfos.map{ case (nRows, _, h) => 340 if (h > 0) 341 Set((h, min(log2Ceil(nRows/TageBanks), h))) 342 else 343 Set[FoldedHistoryInfo]() 344 }.reduce(_++_).toSet ++ 345 ITTageTableInfos.map{ case (nRows, h, t) => 346 if (h > 0) 347 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 348 else 349 Set[FoldedHistoryInfo]() 350 }.reduce(_++_) ++ 351 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 352 ).toList 353 354 355 356 val CacheLineSize = coreParams.CacheLineSize 357 val CacheLineHalfWord = CacheLineSize / 16 358 val ExtHistoryLength = HistoryLength + 64 359 val IBufSize = coreParams.IBufSize 360 val DecodeWidth = coreParams.DecodeWidth 361 val RenameWidth = coreParams.RenameWidth 362 val CommitWidth = coreParams.CommitWidth 363 val FtqSize = coreParams.FtqSize 364 val IssQueSize = coreParams.IssQueSize 365 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 366 val NRPhyRegs = coreParams.NRPhyRegs 367 val PhyRegIdxWidth = log2Up(NRPhyRegs) 368 val RobSize = coreParams.RobSize 369 val IntRefCounterWidth = log2Ceil(RobSize) 370 val LoadQueueSize = coreParams.LoadQueueSize 371 val StoreQueueSize = coreParams.StoreQueueSize 372 val dpParams = coreParams.dpParams 373 val exuParameters = coreParams.exuParameters 374 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 375 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 376 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 377 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 378 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 379 val LoadPipelineWidth = coreParams.LoadPipelineWidth 380 val StorePipelineWidth = coreParams.StorePipelineWidth 381 val StoreBufferSize = coreParams.StoreBufferSize 382 val StoreBufferThreshold = coreParams.StoreBufferThreshold 383 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 384 val EnableFastForward = coreParams.EnableFastForward 385 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 386 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 387 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 388 val RefillSize = coreParams.RefillSize 389 val asidLen = coreParams.MMUAsidLen 390 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 391 val refillBothTlb = coreParams.refillBothTlb 392 val itlbParams = coreParams.itlbParameters 393 val ldtlbParams = coreParams.ldtlbParameters 394 val sttlbParams = coreParams.sttlbParameters 395 val btlbParams = coreParams.btlbParameters 396 val l2tlbParams = coreParams.l2tlbParameters 397 val NumPerfCounters = coreParams.NumPerfCounters 398 399 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 400 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 401 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 402 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 403 404 val instBytes = if (HasCExtension) 2 else 4 405 val instOffsetBits = log2Ceil(instBytes) 406 407 val icacheParameters = coreParams.icacheParameters 408 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 409 410 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 411 // for constrained LR/SC loop 412 val LRSCCycles = 64 413 // for lr storm 414 val LRSCBackOff = 8 415 416 // cache hierarchy configurations 417 val l1BusDataWidth = 256 418 419 // load violation predict 420 val ResetTimeMax2Pow = 20 //1078576 421 val ResetTimeMin2Pow = 10 //1024 422 // wait table parameters 423 val WaitTableSize = 1024 424 val MemPredPCWidth = log2Up(WaitTableSize) 425 val LWTUse2BitCounter = true 426 // store set parameters 427 val SSITSize = WaitTableSize 428 val LFSTSize = 32 429 val SSIDWidth = log2Up(LFSTSize) 430 val LFSTWidth = 4 431 val StoreSetEnable = true // LWT will be disabled if SS is enabled 432 433 val loadExuConfigs = coreParams.loadExuConfigs 434 val storeExuConfigs = coreParams.storeExuConfigs 435 436 val intExuConfigs = coreParams.intExuConfigs 437 438 val fpExuConfigs = coreParams.fpExuConfigs 439 440 val exuConfigs = coreParams.exuConfigs 441 442 val PCntIncrStep: Int = 6 443 val numPCntHc: Int = 25 444 val numPCntPtw: Int = 19 445 446 val numCSRPCntFrontend = 8 447 val numCSRPCntCtrl = 8 448 val numCSRPCntLsu = 8 449 val numCSRPCntHc = 5 450} 451