1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 512, 65 UbtbSize: Int = 1024, 66 FtbSize: Int = 2048, 67 RasSize: Int = 32, 68 CacheLineSize: Int = 512, 69 FtbWays: Int = 4, 70 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 71 // Sets Hist Tag 72 Seq(( 128*8, 2, 10), 73 ( 128*8, 8, 10), 74 ( 128*8, 12, 10), 75 ( 128*8, 16, 10), 76 ( 128*8, 28, 10), 77 ( 128*8, 54, 10), 78 ( 128*8, 119, 10), 79 ( 128*8, 256, 10)), 80 TageBanks: Int = 2, 81 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 82 // Sets Hist Tag 83 Seq(( 512, 0, 0), 84 ( 256, 4, 9), 85 ( 256, 8, 9), 86 ( 512, 12, 9), 87 ( 512, 16, 9), 88 ( 512, 32, 9)), 89 SCNRows: Int = 512, 90 SCNTables: Int = 4, 91 SCCtrBits: Int = 6, 92 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 93 numBr: Int = 2, 94 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 95 ((resp_in: BranchPredictionResp, p: Parameters) => { 96 // val loop = Module(new LoopPredictor) 97 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 98 // else Module(new Tage) } 99 // else { Module(new FakeTage) }) 100 val ftb = Module(new FTB()(p)) 101 val ubtb = Module(new MicroBTB()(p)) 102 val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 // val tage = Module(new Tage()(p)) 107 // val fake = Module(new FakePredictor()(p)) 108 109 // val preds = Seq(loop, tage, btb, ubtb, bim) 110 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 bim.io.in.bits.resp_in(0) := resp_in 119 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 120 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 121 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 122 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 123 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 124 125 (preds, ras.io.out.resp) 126 }), 127 IBufSize: Int = 48, 128 DecodeWidth: Int = 6, 129 RenameWidth: Int = 6, 130 CommitWidth: Int = 6, 131 FtqSize: Int = 64, 132 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 133 IssQueSize: Int = 16, 134 NRPhyRegs: Int = 192, 135 LoadQueueSize: Int = 80, 136 StoreQueueSize: Int = 64, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 LoadPipelineWidth: Int = 2, 158 StorePipelineWidth: Int = 2, 159 StoreBufferSize: Int = 16, 160 StoreBufferThreshold: Int = 7, 161 EnableLoadToLoadForward: Boolean = false, 162 EnableFastForward: Boolean = false, 163 EnableLdVioCheckAfterReset: Boolean = true, 164 RefillSize: Int = 512, 165 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 166 itlbParameters: TLBParameters = TLBParameters( 167 name = "itlb", 168 fetchi = true, 169 useDmode = false, 170 sameCycle = false, 171 missSameCycle = true, 172 normalNWays = 32, 173 normalReplacer = Some("plru"), 174 superNWays = 4, 175 superReplacer = Some("plru"), 176 shouldBlock = true 177 ), 178 ldtlbParameters: TLBParameters = TLBParameters( 179 name = "ldtlb", 180 normalNSets = 128, 181 normalNWays = 1, 182 normalAssociative = "sa", 183 normalReplacer = Some("setplru"), 184 superNWays = 8, 185 normalAsVictim = true, 186 outReplace = true, 187 saveLevel = true 188 ), 189 sttlbParameters: TLBParameters = TLBParameters( 190 name = "sttlb", 191 normalNSets = 128, 192 normalNWays = 1, 193 normalAssociative = "sa", 194 normalReplacer = Some("setplru"), 195 superNWays = 8, 196 normalAsVictim = true, 197 outReplace = true, 198 saveLevel = true 199 ), 200 refillBothTlb: Boolean = false, 201 btlbParameters: TLBParameters = TLBParameters( 202 name = "btlb", 203 normalNSets = 1, 204 normalNWays = 64, 205 superNWays = 4, 206 ), 207 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 208 NumPerfCounters: Int = 16, 209 icacheParameters: ICacheParameters = ICacheParameters( 210 tagECC = Some("parity"), 211 dataECC = Some("parity"), 212 replacer = Some("setplru"), 213 nMissEntries = 2, 214 nReleaseEntries = 2 215 ), 216 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 217 tagECC = Some("secded"), 218 dataECC = Some("secded"), 219 replacer = Some("setplru"), 220 nMissEntries = 16, 221 nProbeEntries = 8, 222 nReleaseEntries = 18 223 )), 224 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 225 name = "l2", 226 level = 2, 227 ways = 8, 228 sets = 1024, // default 512KB L2 229 prefetch = Some(huancun.prefetch.BOPParameters()) 230 )), 231 L2NBanks: Int = 1, 232 usePTWRepeater: Boolean = false, 233 softPTW: Boolean = false // dpi-c debug only 234){ 235 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 236 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 237 238 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 239 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 240 241 val fpExuConfigs = 242 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 243 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 244 245 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 246} 247 248case object DebugOptionsKey extends Field[DebugOptions] 249 250case class DebugOptions 251( 252 FPGAPlatform: Boolean = false, 253 EnableDifftest: Boolean = false, 254 AlwaysBasicDiff: Boolean = true, 255 EnableDebug: Boolean = false, 256 EnablePerfDebug: Boolean = true, 257 UseDRAMSim: Boolean = false 258) 259 260trait HasXSParameter { 261 262 implicit val p: Parameters 263 264 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 265 266 val coreParams = p(XSCoreParamsKey) 267 val env = p(DebugOptionsKey) 268 269 val XLEN = coreParams.XLEN 270 val minFLen = 32 271 val fLen = 64 272 def xLen = XLEN 273 274 val HasMExtension = coreParams.HasMExtension 275 val HasCExtension = coreParams.HasCExtension 276 val HasDiv = coreParams.HasDiv 277 val HasIcache = coreParams.HasICache 278 val HasDcache = coreParams.HasDCache 279 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 280 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 281 val AsidLength = coreParams.AsidLength 282 val AddrBytes = AddrBits / 8 // unused 283 val DataBits = XLEN 284 val DataBytes = DataBits / 8 285 val HasFPU = coreParams.HasFPU 286 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 287 val FetchWidth = coreParams.FetchWidth 288 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 289 val EnableBPU = coreParams.EnableBPU 290 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 291 val EnableRAS = coreParams.EnableRAS 292 val EnableLB = coreParams.EnableLB 293 val EnableLoop = coreParams.EnableLoop 294 val EnableSC = coreParams.EnableSC 295 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 296 val HistoryLength = coreParams.HistoryLength 297 val UbtbGHRLength = log2Ceil(coreParams.UbtbSize) 298 val UbtbSize = coreParams.UbtbSize 299 val FtbSize = coreParams.FtbSize 300 val FtbWays = coreParams.FtbWays 301 val RasSize = coreParams.RasSize 302 303 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 304 coreParams.branchPredictor(resp_in, p) 305 } 306 val numBr = coreParams.numBr 307 val TageTableInfos = coreParams.TageTableInfos 308 309 310 val BankTageTableInfos = (0 until numBr).map(i => 311 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 312 ) 313 val TageBanks = coreParams.TageBanks 314 val SCNRows = coreParams.SCNRows 315 val SCCtrBits = coreParams.SCCtrBits 316 val BankSCHistLens = Seq.fill(numBr)(coreParams.SCHistLens) 317 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 318 319 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 320 case (ntable, histlens) => 321 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 322 } 323 val ITTageTableInfos = coreParams.ITTageTableInfos 324 type FoldedHistoryInfo = Tuple2[Int, Int] 325 val foldedGHistInfos = 326 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 327 if (h > 0) 328 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 329 else 330 Set[FoldedHistoryInfo]() 331 }.reduce(_++_)).toSet ++ 332 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 333 if (h > 0) 334 Set((h, min(log2Ceil(nRows/TageBanks), h))) 335 else 336 Set[FoldedHistoryInfo]() 337 }.reduce(_++_)).toSet ++ 338 ITTageTableInfos.map{ case (nRows, h, t) => 339 if (h > 0) 340 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 341 else 342 Set[FoldedHistoryInfo]() 343 }.reduce(_++_) ++ 344 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 345 ).toList 346 347 val CacheLineSize = coreParams.CacheLineSize 348 val CacheLineHalfWord = CacheLineSize / 16 349 val ExtHistoryLength = HistoryLength + 64 350 val IBufSize = coreParams.IBufSize 351 val DecodeWidth = coreParams.DecodeWidth 352 val RenameWidth = coreParams.RenameWidth 353 val CommitWidth = coreParams.CommitWidth 354 val FtqSize = coreParams.FtqSize 355 val IssQueSize = coreParams.IssQueSize 356 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 357 val NRPhyRegs = coreParams.NRPhyRegs 358 val PhyRegIdxWidth = log2Up(NRPhyRegs) 359 val RobSize = coreParams.RobSize 360 val IntRefCounterWidth = log2Ceil(RobSize) 361 val LoadQueueSize = coreParams.LoadQueueSize 362 val StoreQueueSize = coreParams.StoreQueueSize 363 val dpParams = coreParams.dpParams 364 val exuParameters = coreParams.exuParameters 365 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 366 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 367 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 368 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 369 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 370 val LoadPipelineWidth = coreParams.LoadPipelineWidth 371 val StorePipelineWidth = coreParams.StorePipelineWidth 372 val StoreBufferSize = coreParams.StoreBufferSize 373 val StoreBufferThreshold = coreParams.StoreBufferThreshold 374 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 375 val EnableFastForward = coreParams.EnableFastForward 376 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 377 val RefillSize = coreParams.RefillSize 378 val asidLen = coreParams.MMUAsidLen 379 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 380 val refillBothTlb = coreParams.refillBothTlb 381 val itlbParams = coreParams.itlbParameters 382 val ldtlbParams = coreParams.ldtlbParameters 383 val sttlbParams = coreParams.sttlbParameters 384 val btlbParams = coreParams.btlbParameters 385 val l2tlbParams = coreParams.l2tlbParameters 386 val NumPerfCounters = coreParams.NumPerfCounters 387 388 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 389 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 390 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 391 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 392 393 val instBytes = if (HasCExtension) 2 else 4 394 val instOffsetBits = log2Ceil(instBytes) 395 396 val icacheParameters = coreParams.icacheParameters 397 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 398 399 val LRSCCycles = 100 400 401 // cache hierarchy configurations 402 val l1BusDataWidth = 256 403 404 // load violation predict 405 val ResetTimeMax2Pow = 20 //1078576 406 val ResetTimeMin2Pow = 10 //1024 407 // wait table parameters 408 val WaitTableSize = 1024 409 val MemPredPCWidth = log2Up(WaitTableSize) 410 val LWTUse2BitCounter = true 411 // store set parameters 412 val SSITSize = WaitTableSize 413 val LFSTSize = 32 414 val SSIDWidth = log2Up(LFSTSize) 415 val LFSTWidth = 4 416 val StoreSetEnable = true // LWT will be disabled if SS is enabled 417 418 val loadExuConfigs = coreParams.loadExuConfigs 419 val storeExuConfigs = coreParams.storeExuConfigs 420 421 val intExuConfigs = coreParams.intExuConfigs 422 423 val fpExuConfigs = coreParams.fpExuConfigs 424 425 val exuConfigs = coreParams.exuConfigs 426 427 val PCntIncrStep: Int = 6 428 val numPCntHc: Int = 25 429 val numPCntPtw: Int = 19 430 431 val numCSRPCntFrontend = 8 432 val numCSRPCntCtrl = 8 433 val numCSRPCntLsu = 8 434 val numCSRPCntHc = 5 435} 436