1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 RasSpecSize: Int = 64, 91 RasCtrSize: Int = 8, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 IBufSize: Int = 48, 145 DecodeWidth: Int = 6, 146 RenameWidth: Int = 6, 147 CommitWidth: Int = 6, 148 MaxUopSize: Int = 65, 149 EnableRenameSnapshot: Boolean = true, 150 RenameSnapshotNum: Int = 4, 151 FtqSize: Int = 64, 152 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 153 IntLogicRegs: Int = 32, 154 FpLogicRegs: Int = 33, 155 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 156 VCONFIG_IDX: Int = 32, 157 NRPhyRegs: Int = 192, 158 VirtualLoadQueueSize: Int = 80, 159 LoadQueueRARSize: Int = 80, 160 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 161 RollbackGroupSize: Int = 8, 162 LoadQueueReplaySize: Int = 72, 163 LoadUncacheBufferSize: Int = 20, 164 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 165 StoreQueueSize: Int = 64, 166 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 167 StoreQueueForwardWithMask: Boolean = true, 168 VlsQueueSize: Int = 8, 169 RobSize: Int = 256, 170 RabSize: Int = 256, 171 IssueQueueSize: Int = 32, 172 dpParams: DispatchParameters = DispatchParameters( 173 IntDqSize = 16, 174 FpDqSize = 16, 175 LsDqSize = 16, 176 IntDqDeqWidth = 6, 177 FpDqDeqWidth = 6, 178 LsDqDeqWidth = 6, 179 ), 180 intPreg: PregParams = IntPregParams( 181 numEntries = 192, 182 numRead = None, 183 numWrite = None, 184 ), 185 vfPreg: VfPregParams = VfPregParams( 186 numEntries = 192, 187 numRead = None, 188 numWrite = None, 189 ), 190 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 191 LoadPipelineWidth: Int = 2, 192 StorePipelineWidth: Int = 2, 193 VecMemSrcInWidth: Int = 2, 194 VecMemInstWbWidth: Int = 1, 195 VecMemDispatchWidth: Int = 1, 196 StoreBufferSize: Int = 16, 197 StoreBufferThreshold: Int = 7, 198 EnsbufferWidth: Int = 2, 199 UncacheBufferSize: Int = 4, 200 EnableLoadToLoadForward: Boolean = true, 201 EnableFastForward: Boolean = true, 202 EnableLdVioCheckAfterReset: Boolean = true, 203 EnableSoftPrefetchAfterReset: Boolean = true, 204 EnableCacheErrorAfterReset: Boolean = true, 205 EnableAccurateLoadError: Boolean = true, 206 EnableUncacheWriteOutstanding: Boolean = false, 207 EnableStorePrefetchAtIssue: Boolean = false, 208 EnableStorePrefetchAtCommit: Boolean = false, 209 EnableAtCommitMissTrigger: Boolean = true, 210 EnableStorePrefetchSMS: Boolean = false, 211 EnableStorePrefetchSPB: Boolean = false, 212 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 213 ReSelectLen: Int = 7, // load replay queue replay select counter len 214 iwpuParameters: WPUParameters = WPUParameters( 215 enWPU = false, 216 algoName = "mmru", 217 isICache = true, 218 ), 219 dwpuParameters: WPUParameters = WPUParameters( 220 enWPU = false, 221 algoName = "mmru", 222 enCfPred = false, 223 isICache = false, 224 ), 225 itlbParameters: TLBParameters = TLBParameters( 226 name = "itlb", 227 fetchi = true, 228 useDmode = false, 229 NWays = 48, 230 ), 231 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 232 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 233 ldtlbParameters: TLBParameters = TLBParameters( 234 name = "ldtlb", 235 NWays = 48, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 sttlbParameters: TLBParameters = TLBParameters( 242 name = "sttlb", 243 NWays = 48, 244 outReplace = false, 245 partialStaticPMP = true, 246 outsideRecvFlush = true, 247 saveLevel = true 248 ), 249 pftlbParameters: TLBParameters = TLBParameters( 250 name = "pftlb", 251 NWays = 48, 252 outReplace = false, 253 partialStaticPMP = true, 254 outsideRecvFlush = true, 255 saveLevel = true 256 ), 257 refillBothTlb: Boolean = false, 258 btlbParameters: TLBParameters = TLBParameters( 259 name = "btlb", 260 NWays = 48, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 32, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18, 281 nMaxPrefetchEntry = 6, 282 )), 283 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 284 name = "l2", 285 ways = 8, 286 sets = 1024, // default 512KB L2 287 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 288 )), 289 L2NBanks: Int = 1, 290 usePTWRepeater: Boolean = false, 291 softTLB: Boolean = false, // dpi-c l1tlb debug only 292 softPTW: Boolean = false, // dpi-c l2tlb debug only 293 softPTWDelay: Int = 1 294){ 295 def vlWidth = log2Up(VLEN) + 1 296 297 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 298 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 299 300 val intSchdParams = { 301 implicit val schdType: SchedulerType = IntScheduler() 302 SchdBlockParams(Seq( 303 IssueBlockParams(Seq( 304 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 305 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 306 ), numEntries = IssueQueueSize, numEnq = 2), 307 IssueBlockParams(Seq( 308 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 309 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 310 ), numEntries = IssueQueueSize, numEnq = 2), 311 IssueBlockParams(Seq( 312 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 313 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 314 ), numEntries = IssueQueueSize, numEnq = 2), 315 IssueBlockParams(Seq( 316 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 317 ), numEntries = IssueQueueSize, numEnq = 2), 318 IssueBlockParams(Seq( 319 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 320 ), numEntries = IssueQueueSize, numEnq = 2), 321 ), 322 numPregs = intPreg.numEntries, 323 numDeqOutside = 0, 324 schdType = schdType, 325 rfDataWidth = intPreg.dataCfg.dataWidth, 326 numUopIn = dpParams.IntDqDeqWidth, 327 ) 328 } 329 val vfSchdParams = { 330 implicit val schdType: SchedulerType = VfScheduler() 331 SchdBlockParams(Seq( 332 IssueBlockParams(Seq( 333 ExeUnitParams("FEX0", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(12, 0)), Seq(VfRD(13, 0)))), 334 ), numEntries = IssueQueueSize, numEnq = 2), 335 IssueBlockParams(Seq( 336 ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 337 ), numEntries = IssueQueueSize, numEnq = 2), 338 IssueBlockParams(Seq( 339 ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 2, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 340 ExeUnitParams("VEX2", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 3, 0), IntWB(port = 9, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 341 ), numEntries = IssueQueueSize, numEnq = 2), 342 IssueBlockParams(Seq( 343 ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 344 ), numEntries = IssueQueueSize, numEnq = 2), 345 IssueBlockParams(Seq( 346 ExeUnitParams("VEX4", Seq(VfcvtCfg), Seq(VfWB(port = 8, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(10, 1)), Seq(VfRD(11, 1)))), 347 ), numEntries = IssueQueueSize, numEnq = 2), 348 ), 349 numPregs = vfPreg.numEntries, 350 numDeqOutside = 0, 351 schdType = schdType, 352 rfDataWidth = vfPreg.dataCfg.dataWidth, 353 numUopIn = dpParams.FpDqDeqWidth, 354 ) 355 } 356 357 val memSchdParams = { 358 implicit val schdType: SchedulerType = MemScheduler() 359 val rfDataWidth = 64 360 361 SchdBlockParams(Seq( 362 IssueBlockParams(Seq( 363 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 364 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 365 ), numEntries = IssueQueueSize, numEnq = 2), 366 IssueBlockParams(Seq( 367 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(10, 0)), Seq(Seq(IntRD(12, 0)))), 368 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(11, 0)), Seq(Seq(IntRD(13, 0)))), 369 ), numEntries = IssueQueueSize, numEnq = 2), 370 IssueBlockParams(Seq( 371 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 372 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 373 ), numEntries = IssueQueueSize, numEnq = 2), 374 IssueBlockParams(Seq( 375 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 376 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 377 ), numEntries = IssueQueueSize, numEnq = 2), 378 ), 379 numPregs = intPreg.numEntries max vfPreg.numEntries, 380 numDeqOutside = 0, 381 schdType = schdType, 382 rfDataWidth = rfDataWidth, 383 numUopIn = dpParams.LsDqDeqWidth, 384 ) 385 } 386 387 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 388 389 def iqWakeUpParams = { 390 Seq( 391 WakeUpConfig( 392 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "LDU0", "LDU1") -> 393 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "LDU0", "LDU1", "STA0", "STA1", "STD0", "STD1") 394 ), 395 WakeUpConfig(Seq("IMISC0") -> Seq("FEX0")), 396 ).flatten 397 } 398 399 def backendParams: BackendParams = backend.BackendParams( 400 Map( 401 IntScheduler() -> intSchdParams, 402 VfScheduler() -> vfSchdParams, 403 MemScheduler() -> memSchdParams, 404 ), 405 Seq( 406 intPreg, 407 vfPreg, 408 ), 409 iqWakeUpParams, 410 ) 411} 412 413case object DebugOptionsKey extends Field[DebugOptions] 414 415case class DebugOptions 416( 417 FPGAPlatform: Boolean = false, 418 EnableDifftest: Boolean = false, 419 AlwaysBasicDiff: Boolean = true, 420 EnableDebug: Boolean = false, 421 EnablePerfDebug: Boolean = true, 422 UseDRAMSim: Boolean = false, 423 EnableConstantin: Boolean = false, 424 EnableChiselDB: Boolean = false, 425 AlwaysBasicDB: Boolean = true, 426 EnableTopDown: Boolean = false, 427 EnableRollingDB: Boolean = false 428) 429 430trait HasXSParameter { 431 432 implicit val p: Parameters 433 434 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 435 436 val coreParams = p(XSCoreParamsKey) 437 val env = p(DebugOptionsKey) 438 439 val XLEN = coreParams.XLEN 440 val VLEN = coreParams.VLEN 441 val ELEN = coreParams.ELEN 442 val minFLen = 32 443 val fLen = 64 444 def xLen = XLEN 445 446 val HasMExtension = coreParams.HasMExtension 447 val HasCExtension = coreParams.HasCExtension 448 val HasDiv = coreParams.HasDiv 449 val HasIcache = coreParams.HasICache 450 val HasDcache = coreParams.HasDCache 451 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 452 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 453 val AsidLength = coreParams.AsidLength 454 val ReSelectLen = coreParams.ReSelectLen 455 val AddrBytes = AddrBits / 8 // unused 456 val DataBits = XLEN 457 val DataBytes = DataBits / 8 458 val VDataBytes = VLEN / 8 459 val HasFPU = coreParams.HasFPU 460 val HasVPU = coreParams.HasVPU 461 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 462 val FetchWidth = coreParams.FetchWidth 463 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 464 val EnableBPU = coreParams.EnableBPU 465 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 466 val EnableRAS = coreParams.EnableRAS 467 val EnableLB = coreParams.EnableLB 468 val EnableLoop = coreParams.EnableLoop 469 val EnableSC = coreParams.EnableSC 470 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 471 val HistoryLength = coreParams.HistoryLength 472 val EnableGHistDiff = coreParams.EnableGHistDiff 473 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 474 val UbtbGHRLength = coreParams.UbtbGHRLength 475 val UbtbSize = coreParams.UbtbSize 476 val EnableFauFTB = coreParams.EnableFauFTB 477 val FtbSize = coreParams.FtbSize 478 val FtbWays = coreParams.FtbWays 479 val RasSize = coreParams.RasSize 480 val RasSpecSize = coreParams.RasSpecSize 481 val RasCtrSize = coreParams.RasCtrSize 482 483 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 484 coreParams.branchPredictor(resp_in, p) 485 } 486 val numBr = coreParams.numBr 487 val TageTableInfos = coreParams.TageTableInfos 488 val TageBanks = coreParams.numBr 489 val SCNRows = coreParams.SCNRows 490 val SCCtrBits = coreParams.SCCtrBits 491 val SCHistLens = coreParams.SCHistLens 492 val SCNTables = coreParams.SCNTables 493 494 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 495 case ((n, cb), h) => (n, cb, h) 496 } 497 val ITTageTableInfos = coreParams.ITTageTableInfos 498 type FoldedHistoryInfo = Tuple2[Int, Int] 499 val foldedGHistInfos = 500 (TageTableInfos.map{ case (nRows, h, t) => 501 if (h > 0) 502 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 503 else 504 Set[FoldedHistoryInfo]() 505 }.reduce(_++_).toSet ++ 506 SCTableInfos.map{ case (nRows, _, h) => 507 if (h > 0) 508 Set((h, min(log2Ceil(nRows/TageBanks), h))) 509 else 510 Set[FoldedHistoryInfo]() 511 }.reduce(_++_).toSet ++ 512 ITTageTableInfos.map{ case (nRows, h, t) => 513 if (h > 0) 514 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 515 else 516 Set[FoldedHistoryInfo]() 517 }.reduce(_++_) ++ 518 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 519 ).toList 520 521 522 523 val CacheLineSize = coreParams.CacheLineSize 524 val CacheLineHalfWord = CacheLineSize / 16 525 val ExtHistoryLength = HistoryLength + 64 526 val IBufSize = coreParams.IBufSize 527 val DecodeWidth = coreParams.DecodeWidth 528 val RenameWidth = coreParams.RenameWidth 529 val CommitWidth = coreParams.CommitWidth 530 val MaxUopSize = coreParams.MaxUopSize 531 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 532 val RenameSnapshotNum = coreParams.RenameSnapshotNum 533 val FtqSize = coreParams.FtqSize 534 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 535 val IntLogicRegs = coreParams.IntLogicRegs 536 val FpLogicRegs = coreParams.FpLogicRegs 537 val VecLogicRegs = coreParams.VecLogicRegs 538 val VCONFIG_IDX = coreParams.VCONFIG_IDX 539 val IntPhyRegs = coreParams.intPreg.numEntries 540 val VfPhyRegs = coreParams.vfPreg.numEntries 541 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 542 val RobSize = coreParams.RobSize 543 val RabSize = coreParams.RabSize 544 val IntRefCounterWidth = log2Ceil(RobSize) 545 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 546 val LoadQueueRARSize = coreParams.LoadQueueRARSize 547 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 548 val RollbackGroupSize = coreParams.RollbackGroupSize 549 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 550 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 551 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 552 val StoreQueueSize = coreParams.StoreQueueSize 553 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 554 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 555 val VlsQueueSize = coreParams.VlsQueueSize 556 val dpParams = coreParams.dpParams 557 558 def backendParams: BackendParams = coreParams.backendParams 559 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 560 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 561 val LoadPipelineWidth = coreParams.LoadPipelineWidth 562 val StorePipelineWidth = coreParams.StorePipelineWidth 563 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 564 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 565 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 566 val StoreBufferSize = coreParams.StoreBufferSize 567 val StoreBufferThreshold = coreParams.StoreBufferThreshold 568 val EnsbufferWidth = coreParams.EnsbufferWidth 569 val UncacheBufferSize = coreParams.UncacheBufferSize 570 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 571 val EnableFastForward = coreParams.EnableFastForward 572 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 573 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 574 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 575 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 576 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 577 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 578 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 579 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 580 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 581 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 582 val asidLen = coreParams.MMUAsidLen 583 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 584 val refillBothTlb = coreParams.refillBothTlb 585 val iwpuParam = coreParams.iwpuParameters 586 val dwpuParam = coreParams.dwpuParameters 587 val itlbParams = coreParams.itlbParameters 588 val ldtlbParams = coreParams.ldtlbParameters 589 val sttlbParams = coreParams.sttlbParameters 590 val pftlbParams = coreParams.pftlbParameters 591 val btlbParams = coreParams.btlbParameters 592 val l2tlbParams = coreParams.l2tlbParameters 593 val NumPerfCounters = coreParams.NumPerfCounters 594 595 val instBytes = if (HasCExtension) 2 else 4 596 val instOffsetBits = log2Ceil(instBytes) 597 598 val icacheParameters = coreParams.icacheParameters 599 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 600 601 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 602 // for constrained LR/SC loop 603 val LRSCCycles = 64 604 // for lr storm 605 val LRSCBackOff = 8 606 607 // cache hierarchy configurations 608 val l1BusDataWidth = 256 609 610 // load violation predict 611 val ResetTimeMax2Pow = 20 //1078576 612 val ResetTimeMin2Pow = 10 //1024 613 // wait table parameters 614 val WaitTableSize = 1024 615 val MemPredPCWidth = log2Up(WaitTableSize) 616 val LWTUse2BitCounter = true 617 // store set parameters 618 val SSITSize = WaitTableSize 619 val LFSTSize = 32 620 val SSIDWidth = log2Up(LFSTSize) 621 val LFSTWidth = 4 622 val StoreSetEnable = true // LWT will be disabled if SS is enabled 623 val LFSTEnable = false 624 625 val PCntIncrStep: Int = 6 626 val numPCntHc: Int = 25 627 val numPCntPtw: Int = 19 628 629 val numCSRPCntFrontend = 8 630 val numCSRPCntCtrl = 8 631 val numCSRPCntLsu = 8 632 val numCSRPCntHc = 5 633} 634