1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableClockGate: Boolean = true, 82 EnableJal: Boolean = false, 83 EnableFauFTB: Boolean = true, 84 UbtbGHRLength: Int = 4, 85 // HistoryLength: Int = 512, 86 EnableGHistDiff: Boolean = true, 87 EnableCommitGHistDiff: Boolean = true, 88 UbtbSize: Int = 256, 89 FtbSize: Int = 2048, 90 RasSize: Int = 16, 91 RasSpecSize: Int = 32, 92 RasCtrSize: Int = 3, 93 CacheLineSize: Int = 512, 94 FtbWays: Int = 4, 95 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 // Seq(( 2048, 2, 8), 98 // ( 2048, 9, 8), 99 // ( 2048, 13, 8), 100 // ( 2048, 20, 8), 101 // ( 2048, 26, 8), 102 // ( 2048, 44, 8), 103 // ( 2048, 73, 8), 104 // ( 2048, 256, 8)), 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 122 ((resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val ubtb =Module(new FauFTB()(p)) 125 // val bim = Module(new BIM()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(ubtb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 // ubtb.io.resp_in(0) := resp_in 133 // bim.io.resp_in(0) := ubtb.io.resp 134 // btb.io.resp_in(0) := bim.io.resp 135 // tage.io.resp_in(0) := btb.io.resp 136 // loop.io.resp_in(0) := tage.io.resp 137 ubtb.io.in.bits.resp_in(0) := resp_in 138 tage.io.in.bits.resp_in(0) := ubtb.io.out 139 ftb.io.in.bits.resp_in(0) := tage.io.out 140 ittage.io.in.bits.resp_in(0) := ftb.io.out 141 ras.io.in.bits.resp_in(0) := ittage.io.out 142 143 (preds, ras.io.out) 144 }), 145 ICacheECCForceError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 159 VCONFIG_IDX: Int = 32, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 vfPreg: VfPregParams = VfPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 196 LoadPipelineWidth: Int = 3, 197 StorePipelineWidth: Int = 2, 198 VecLoadPipelineWidth: Int = 1, 199 VecStorePipelineWidth: Int = 1, 200 VecMemSrcInWidth: Int = 2, 201 VecMemInstWbWidth: Int = 1, 202 VecMemDispatchWidth: Int = 1, 203 VecMemDispatchMaxNumber: Int = 16, 204 StoreBufferSize: Int = 16, 205 StoreBufferThreshold: Int = 7, 206 EnsbufferWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 1, 211 VLUopWritebackWidth: Int = 1, 212 VSUopWritebackWidth: Int = 1, 213 SplitBufferSize: Int = 8, 214 // ============================== 215 UncacheBufferSize: Int = 4, 216 EnableLoadToLoadForward: Boolean = false, 217 EnableFastForward: Boolean = true, 218 EnableLdVioCheckAfterReset: Boolean = true, 219 EnableSoftPrefetchAfterReset: Boolean = true, 220 EnableCacheErrorAfterReset: Boolean = true, 221 EnableAccurateLoadError: Boolean = true, 222 EnableUncacheWriteOutstanding: Boolean = false, 223 EnableStorePrefetchAtIssue: Boolean = false, 224 EnableStorePrefetchAtCommit: Boolean = false, 225 EnableAtCommitMissTrigger: Boolean = true, 226 EnableStorePrefetchSMS: Boolean = false, 227 EnableStorePrefetchSPB: Boolean = false, 228 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 229 ReSelectLen: Int = 7, // load replay queue replay select counter len 230 iwpuParameters: WPUParameters = WPUParameters( 231 enWPU = false, 232 algoName = "mmru", 233 isICache = true, 234 ), 235 dwpuParameters: WPUParameters = WPUParameters( 236 enWPU = false, 237 algoName = "mmru", 238 enCfPred = false, 239 isICache = false, 240 ), 241 itlbParameters: TLBParameters = TLBParameters( 242 name = "itlb", 243 fetchi = true, 244 useDmode = false, 245 NWays = 48, 246 ), 247 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 248 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 249 ldtlbParameters: TLBParameters = TLBParameters( 250 name = "ldtlb", 251 NWays = 48, 252 outReplace = false, 253 partialStaticPMP = true, 254 outsideRecvFlush = true, 255 saveLevel = true, 256 lgMaxSize = 4 257 ), 258 sttlbParameters: TLBParameters = TLBParameters( 259 name = "sttlb", 260 NWays = 48, 261 outReplace = false, 262 partialStaticPMP = true, 263 outsideRecvFlush = true, 264 saveLevel = true, 265 lgMaxSize = 4 266 ), 267 hytlbParameters: TLBParameters = TLBParameters( 268 name = "hytlb", 269 NWays = 48, 270 outReplace = false, 271 partialStaticPMP = true, 272 outsideRecvFlush = true, 273 saveLevel = true, 274 lgMaxSize = 4 275 ), 276 pftlbParameters: TLBParameters = TLBParameters( 277 name = "pftlb", 278 NWays = 48, 279 outReplace = false, 280 partialStaticPMP = true, 281 outsideRecvFlush = true, 282 saveLevel = true, 283 lgMaxSize = 4 284 ), 285 refillBothTlb: Boolean = false, 286 btlbParameters: TLBParameters = TLBParameters( 287 name = "btlb", 288 NWays = 48, 289 ), 290 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 291 NumPerfCounters: Int = 16, 292 icacheParameters: ICacheParameters = ICacheParameters( 293 tagECC = Some("parity"), 294 dataECC = Some("parity"), 295 replacer = Some("setplru"), 296 nMissEntries = 2, 297 nProbeEntries = 2, 298 nPrefetchEntries = 12, 299 nPrefBufferEntries = 32, 300 ), 301 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 302 tagECC = Some("secded"), 303 dataECC = Some("secded"), 304 replacer = Some("setplru"), 305 nMissEntries = 16, 306 nProbeEntries = 8, 307 nReleaseEntries = 18, 308 nMaxPrefetchEntry = 6, 309 )), 310 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 311 name = "l2", 312 ways = 8, 313 sets = 1024, // default 512KB L2 314 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 315 )), 316 L2NBanks: Int = 1, 317 usePTWRepeater: Boolean = false, 318 softTLB: Boolean = false, // dpi-c l1tlb debug only 319 softPTW: Boolean = false, // dpi-c l2tlb debug only 320 softPTWDelay: Int = 1 321){ 322 def vlWidth = log2Up(VLEN) + 1 323 324 /** 325 * the minimum element length of vector elements 326 */ 327 val minVecElen: Int = 8 328 329 /** 330 * the maximum number of elements in vector register 331 */ 332 val maxElemPerVreg: Int = VLEN / minVecElen 333 334 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 335 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 336 337 val intSchdParams = { 338 implicit val schdType: SchedulerType = IntScheduler() 339 SchdBlockParams(Seq( 340 IssueBlockParams(Seq( 341 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 342 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 343 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 344 IssueBlockParams(Seq( 345 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 346 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 347 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 348 IssueBlockParams(Seq( 349 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 350 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 351 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 352 IssueBlockParams(Seq( 353 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 354 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 355 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 356 ), 357 numPregs = intPreg.numEntries, 358 numDeqOutside = 0, 359 schdType = schdType, 360 rfDataWidth = intPreg.dataCfg.dataWidth, 361 numUopIn = dpParams.IntDqDeqWidth, 362 ) 363 } 364 val vfSchdParams = { 365 implicit val schdType: SchedulerType = VfScheduler() 366 SchdBlockParams(Seq( 367 IssueBlockParams(Seq( 368 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VimacCfg), Seq(VfWB(port = 5, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 369 ExeUnitParams("VFEX1", Seq(VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, VSetRvfWvfCfg), Seq(VfWB(port = 6, 1), IntWB(port = 1, 2)), Seq(Seq(VfRD(5, 1)), Seq(VfRD(6, 1)), Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)))), 370 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 371 IssueBlockParams(Seq( 372 ExeUnitParams("VFEX2", Seq(VfaluCfg, VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 373 ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(VfRD(3, 1)), Seq(VfRD(4, 1)))), 374 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 375 ), 376 numPregs = vfPreg.numEntries, 377 numDeqOutside = 0, 378 schdType = schdType, 379 rfDataWidth = vfPreg.dataCfg.dataWidth, 380 numUopIn = dpParams.FpDqDeqWidth, 381 ) 382 } 383 384 val memSchdParams = { 385 implicit val schdType: SchedulerType = MemScheduler() 386 val rfDataWidth = 64 387 388 SchdBlockParams(Seq( 389 IssueBlockParams(Seq( 390 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 391 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 392 IssueBlockParams(Seq( 393 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 394 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 395 IssueBlockParams(Seq( 396 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 397 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 398 IssueBlockParams(Seq( 399 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 400 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 401 IssueBlockParams(Seq( 402 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 403 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 404 IssueBlockParams(Seq( 405 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 406 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 407 IssueBlockParams(Seq( 408 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 IssueBlockParams(Seq( 411 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))), 412 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 413 ), 414 numPregs = intPreg.numEntries max vfPreg.numEntries, 415 numDeqOutside = 0, 416 schdType = schdType, 417 rfDataWidth = rfDataWidth, 418 numUopIn = dpParams.LsDqDeqWidth, 419 ) 420 } 421 422 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 423 424 def iqWakeUpParams = { 425 Seq( 426 WakeUpConfig( 427 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 428 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 429 ), 430 WakeUpConfig( 431 Seq("VFEX0", "VFEX1", "VFEX2") -> 432 Seq("VFEX0", "VFEX1", "VFEX2") 433 ), 434 ).flatten 435 } 436 437 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 438 439 val backendParams: BackendParams = backend.BackendParams( 440 Map( 441 IntScheduler() -> intSchdParams, 442 VfScheduler() -> vfSchdParams, 443 MemScheduler() -> memSchdParams, 444 ), 445 Seq( 446 intPreg, 447 vfPreg, 448 fakeIntPreg 449 ), 450 iqWakeUpParams, 451 ) 452} 453 454case object DebugOptionsKey extends Field[DebugOptions] 455 456case class DebugOptions 457( 458 FPGAPlatform: Boolean = false, 459 EnableDifftest: Boolean = false, 460 AlwaysBasicDiff: Boolean = true, 461 EnableDebug: Boolean = false, 462 EnablePerfDebug: Boolean = true, 463 UseDRAMSim: Boolean = false, 464 EnableConstantin: Boolean = false, 465 EnableChiselDB: Boolean = false, 466 AlwaysBasicDB: Boolean = true, 467 EnableTopDown: Boolean = false, 468 EnableRollingDB: Boolean = false 469) 470 471trait HasXSParameter { 472 473 implicit val p: Parameters 474 475 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 476 477 val coreParams = p(XSCoreParamsKey) 478 val env = p(DebugOptionsKey) 479 480 val XLEN = coreParams.XLEN 481 val VLEN = coreParams.VLEN 482 val ELEN = coreParams.ELEN 483 val minFLen = 32 484 val fLen = 64 485 def xLen = XLEN 486 487 val HasMExtension = coreParams.HasMExtension 488 val HasCExtension = coreParams.HasCExtension 489 val HasDiv = coreParams.HasDiv 490 val HasIcache = coreParams.HasICache 491 val HasDcache = coreParams.HasDCache 492 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 493 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 494 val AsidLength = coreParams.AsidLength 495 val ReSelectLen = coreParams.ReSelectLen 496 val AddrBytes = AddrBits / 8 // unused 497 val DataBits = XLEN 498 val DataBytes = DataBits / 8 499 val VDataBytes = VLEN / 8 500 val HasFPU = coreParams.HasFPU 501 val HasVPU = coreParams.HasVPU 502 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 503 val FetchWidth = coreParams.FetchWidth 504 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 505 val EnableBPU = coreParams.EnableBPU 506 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 507 val EnableRAS = coreParams.EnableRAS 508 val EnableLB = coreParams.EnableLB 509 val EnableLoop = coreParams.EnableLoop 510 val EnableSC = coreParams.EnableSC 511 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 512 val HistoryLength = coreParams.HistoryLength 513 val EnableGHistDiff = coreParams.EnableGHistDiff 514 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 515 val EnableClockGate = coreParams.EnableClockGate 516 val UbtbGHRLength = coreParams.UbtbGHRLength 517 val UbtbSize = coreParams.UbtbSize 518 val EnableFauFTB = coreParams.EnableFauFTB 519 val FtbSize = coreParams.FtbSize 520 val FtbWays = coreParams.FtbWays 521 val RasSize = coreParams.RasSize 522 val RasSpecSize = coreParams.RasSpecSize 523 val RasCtrSize = coreParams.RasCtrSize 524 525 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 526 coreParams.branchPredictor(resp_in, p) 527 } 528 val numBr = coreParams.numBr 529 val TageTableInfos = coreParams.TageTableInfos 530 val TageBanks = coreParams.numBr 531 val SCNRows = coreParams.SCNRows 532 val SCCtrBits = coreParams.SCCtrBits 533 val SCHistLens = coreParams.SCHistLens 534 val SCNTables = coreParams.SCNTables 535 536 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 537 case ((n, cb), h) => (n, cb, h) 538 } 539 val ITTageTableInfos = coreParams.ITTageTableInfos 540 type FoldedHistoryInfo = Tuple2[Int, Int] 541 val foldedGHistInfos = 542 (TageTableInfos.map{ case (nRows, h, t) => 543 if (h > 0) 544 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 545 else 546 Set[FoldedHistoryInfo]() 547 }.reduce(_++_).toSet ++ 548 SCTableInfos.map{ case (nRows, _, h) => 549 if (h > 0) 550 Set((h, min(log2Ceil(nRows/TageBanks), h))) 551 else 552 Set[FoldedHistoryInfo]() 553 }.reduce(_++_).toSet ++ 554 ITTageTableInfos.map{ case (nRows, h, t) => 555 if (h > 0) 556 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 557 else 558 Set[FoldedHistoryInfo]() 559 }.reduce(_++_) ++ 560 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 561 ).toList 562 563 564 565 val CacheLineSize = coreParams.CacheLineSize 566 val CacheLineHalfWord = CacheLineSize / 16 567 val ExtHistoryLength = HistoryLength + 64 568 val ICacheECCForceError = coreParams.ICacheECCForceError 569 val IBufSize = coreParams.IBufSize 570 val IBufNBank = coreParams.IBufNBank 571 val backendParams: BackendParams = coreParams.backendParams 572 val DecodeWidth = coreParams.DecodeWidth 573 val RenameWidth = coreParams.RenameWidth 574 val CommitWidth = coreParams.CommitWidth 575 val MaxUopSize = coreParams.MaxUopSize 576 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 577 val RenameSnapshotNum = coreParams.RenameSnapshotNum 578 val FtqSize = coreParams.FtqSize 579 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 580 val IntLogicRegs = coreParams.IntLogicRegs 581 val FpLogicRegs = coreParams.FpLogicRegs 582 val VecLogicRegs = coreParams.VecLogicRegs 583 val VCONFIG_IDX = coreParams.VCONFIG_IDX 584 val IntPhyRegs = coreParams.intPreg.numEntries 585 val VfPhyRegs = coreParams.vfPreg.numEntries 586 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 587 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 588 val RobSize = coreParams.RobSize 589 val RabSize = coreParams.RabSize 590 val VTypeBufferSize = coreParams.VTypeBufferSize 591 /** 592 * the minimum element length of vector elements 593 */ 594 val minVecElen: Int = coreParams.minVecElen 595 596 /** 597 * the maximum number of elements in vector register 598 */ 599 val maxElemPerVreg: Int = coreParams.maxElemPerVreg 600 601 val IntRefCounterWidth = log2Ceil(RobSize) 602 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 603 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 604 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 605 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 606 val LoadQueueRARSize = coreParams.LoadQueueRARSize 607 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 608 val RollbackGroupSize = coreParams.RollbackGroupSize 609 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 610 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 611 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 612 val StoreQueueSize = coreParams.StoreQueueSize 613 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 614 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 615 val VlsQueueSize = coreParams.VlsQueueSize 616 val dpParams = coreParams.dpParams 617 618 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 619 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 620 621 val NumRedirect = backendParams.numRedirect 622 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 623 val FtqRedirectAheadNum = NumRedirect 624 val LoadPipelineWidth = coreParams.LoadPipelineWidth 625 val StorePipelineWidth = coreParams.StorePipelineWidth 626 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 627 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 628 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 629 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 630 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 631 val VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 632 val StoreBufferSize = coreParams.StoreBufferSize 633 val StoreBufferThreshold = coreParams.StoreBufferThreshold 634 val EnsbufferWidth = coreParams.EnsbufferWidth 635 val VlMergeBufferSize = coreParams.VlMergeBufferSize 636 val VsMergeBufferSize = coreParams.VsMergeBufferSize 637 val UopWritebackWidth = coreParams.UopWritebackWidth 638 val VLUopWritebackWidth = coreParams.VLUopWritebackWidth 639 val VSUopWritebackWidth = coreParams.VSUopWritebackWidth 640 val SplitBufferSize = coreParams.SplitBufferSize 641 val UncacheBufferSize = coreParams.UncacheBufferSize 642 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 643 val EnableFastForward = coreParams.EnableFastForward 644 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 645 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 646 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 647 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 648 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 649 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 650 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 651 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 652 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 653 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 654 val asidLen = coreParams.MMUAsidLen 655 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 656 val refillBothTlb = coreParams.refillBothTlb 657 val iwpuParam = coreParams.iwpuParameters 658 val dwpuParam = coreParams.dwpuParameters 659 val itlbParams = coreParams.itlbParameters 660 val ldtlbParams = coreParams.ldtlbParameters 661 val sttlbParams = coreParams.sttlbParameters 662 val hytlbParams = coreParams.hytlbParameters 663 val pftlbParams = coreParams.pftlbParameters 664 val btlbParams = coreParams.btlbParameters 665 val l2tlbParams = coreParams.l2tlbParameters 666 val NumPerfCounters = coreParams.NumPerfCounters 667 668 val instBytes = if (HasCExtension) 2 else 4 669 val instOffsetBits = log2Ceil(instBytes) 670 671 val icacheParameters = coreParams.icacheParameters 672 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 673 674 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 675 // for constrained LR/SC loop 676 val LRSCCycles = 64 677 // for lr storm 678 val LRSCBackOff = 8 679 680 // cache hierarchy configurations 681 val l1BusDataWidth = 256 682 683 // load violation predict 684 val ResetTimeMax2Pow = 20 //1078576 685 val ResetTimeMin2Pow = 10 //1024 686 // wait table parameters 687 val WaitTableSize = 1024 688 val MemPredPCWidth = log2Up(WaitTableSize) 689 val LWTUse2BitCounter = true 690 // store set parameters 691 val SSITSize = WaitTableSize 692 val LFSTSize = 32 693 val SSIDWidth = log2Up(LFSTSize) 694 val LFSTWidth = 4 695 val StoreSetEnable = true // LWT will be disabled if SS is enabled 696 val LFSTEnable = true 697 698 val PCntIncrStep: Int = 6 699 val numPCntHc: Int = 25 700 val numPCntPtw: Int = 19 701 702 val numCSRPCntFrontend = 8 703 val numCSRPCntCtrl = 8 704 val numCSRPCntLsu = 8 705 val numCSRPCntHc = 5 706 val printEventCoding = true 707 708 // Parameters for Sdtrig extension 709 protected val TriggerNum = 4 710 protected val TriggerChainMaxLength = 2 711} 712