1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 CacheLineSize: Int = 512, 91 FtbWays: Int = 4, 92 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 93 // Sets Hist Tag 94 // Seq(( 2048, 2, 8), 95 // ( 2048, 9, 8), 96 // ( 2048, 13, 8), 97 // ( 2048, 20, 8), 98 // ( 2048, 26, 8), 99 // ( 2048, 44, 8), 100 // ( 2048, 73, 8), 101 // ( 2048, 256, 8)), 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 119 ((resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val ubtb =Module(new FauFTB()(p)) 122 // val bim = Module(new BIM()(p)) 123 val tage = Module(new Tage_SC()(p)) 124 val ras = Module(new RAS()(p)) 125 val ittage = Module(new ITTage()(p)) 126 val preds = Seq(ubtb, tage, ftb, ittage, ras) 127 preds.map(_.io := DontCare) 128 129 // ubtb.io.resp_in(0) := resp_in 130 // bim.io.resp_in(0) := ubtb.io.resp 131 // btb.io.resp_in(0) := bim.io.resp 132 // tage.io.resp_in(0) := btb.io.resp 133 // loop.io.resp_in(0) := tage.io.resp 134 ubtb.io.in.bits.resp_in(0) := resp_in 135 tage.io.in.bits.resp_in(0) := ubtb.io.out 136 ftb.io.in.bits.resp_in(0) := tage.io.out 137 ittage.io.in.bits.resp_in(0) := ftb.io.out 138 ras.io.in.bits.resp_in(0) := ittage.io.out 139 140 (preds, ras.io.out) 141 }), 142 IBufSize: Int = 48, 143 DecodeWidth: Int = 6, 144 RenameWidth: Int = 6, 145 CommitWidth: Int = 6, 146 MaxUopSize: Int = 65, 147 EnableRenameSnapshot: Boolean = true, 148 RenameSnapshotNum: Int = 4, 149 FtqSize: Int = 64, 150 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 151 IntLogicRegs: Int = 32, 152 FpLogicRegs: Int = 33, 153 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 154 VCONFIG_IDX: Int = 32, 155 NRPhyRegs: Int = 192, 156 VirtualLoadQueueSize: Int = 80, 157 LoadQueueRARSize: Int = 80, 158 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 159 RollbackGroupSize: Int = 8, 160 LoadQueueReplaySize: Int = 72, 161 LoadUncacheBufferSize: Int = 20, 162 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 163 StoreQueueSize: Int = 64, 164 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 165 StoreQueueForwardWithMask: Boolean = true, 166 VlsQueueSize: Int = 8, 167 RobSize: Int = 256, 168 RabSize: Int = 256, 169 IssueQueueSize: Int = 32, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 16, 174 IntDqDeqWidth = 6, 175 FpDqDeqWidth = 6, 176 LsDqDeqWidth = 6, 177 ), 178 intPreg: PregParams = IntPregParams( 179 numEntries = 192, 180 numRead = None, 181 numWrite = None, 182 ), 183 vfPreg: VfPregParams = VfPregParams( 184 numEntries = 192, 185 numRead = None, 186 numWrite = None, 187 ), 188 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 189 LoadPipelineWidth: Int = 2, 190 StorePipelineWidth: Int = 2, 191 VecMemSrcInWidth: Int = 2, 192 VecMemInstWbWidth: Int = 1, 193 VecMemDispatchWidth: Int = 1, 194 StoreBufferSize: Int = 16, 195 StoreBufferThreshold: Int = 7, 196 EnsbufferWidth: Int = 2, 197 UncacheBufferSize: Int = 4, 198 EnableLoadToLoadForward: Boolean = true, 199 EnableFastForward: Boolean = true, 200 EnableLdVioCheckAfterReset: Boolean = true, 201 EnableSoftPrefetchAfterReset: Boolean = true, 202 EnableCacheErrorAfterReset: Boolean = true, 203 EnableAccurateLoadError: Boolean = true, 204 EnableUncacheWriteOutstanding: Boolean = false, 205 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 206 ReSelectLen: Int = 7, // load replay queue replay select counter len 207 iwpuParameters: WPUParameters = WPUParameters( 208 enWPU = false, 209 algoName = "mmru", 210 isICache = true, 211 ), 212 dwpuParameters: WPUParameters = WPUParameters( 213 enWPU = false, 214 algoName = "mmru", 215 enCfPred = false, 216 isICache = false, 217 ), 218 itlbParameters: TLBParameters = TLBParameters( 219 name = "itlb", 220 fetchi = true, 221 useDmode = false, 222 normalNWays = 32, 223 normalReplacer = Some("plru"), 224 superNWays = 4, 225 superReplacer = Some("plru") 226 ), 227 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 228 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 229 ldtlbParameters: TLBParameters = TLBParameters( 230 name = "ldtlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 sttlbParameters: TLBParameters = TLBParameters( 243 name = "sttlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 pftlbParameters: TLBParameters = TLBParameters( 256 name = "pftlb", 257 normalNSets = 64, 258 normalNWays = 1, 259 normalAssociative = "sa", 260 normalReplacer = Some("setplru"), 261 superNWays = 16, 262 normalAsVictim = true, 263 outReplace = false, 264 partialStaticPMP = true, 265 outsideRecvFlush = true, 266 saveLevel = true 267 ), 268 refillBothTlb: Boolean = false, 269 btlbParameters: TLBParameters = TLBParameters( 270 name = "btlb", 271 normalNSets = 1, 272 normalNWays = 64, 273 superNWays = 4, 274 ), 275 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 276 NumPerfCounters: Int = 16, 277 icacheParameters: ICacheParameters = ICacheParameters( 278 tagECC = Some("parity"), 279 dataECC = Some("parity"), 280 replacer = Some("setplru"), 281 nMissEntries = 2, 282 nProbeEntries = 2, 283 nPrefetchEntries = 12, 284 nPrefBufferEntries = 64, 285 hasPrefetch = true, 286 ), 287 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 288 tagECC = Some("secded"), 289 dataECC = Some("secded"), 290 replacer = Some("setplru"), 291 nMissEntries = 16, 292 nProbeEntries = 8, 293 nReleaseEntries = 18 294 )), 295 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 296 name = "l2", 297 ways = 8, 298 sets = 1024, // default 512KB L2 299 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 300 )), 301 L2NBanks: Int = 1, 302 usePTWRepeater: Boolean = false, 303 softTLB: Boolean = false, // dpi-c l1tlb debug only 304 softPTW: Boolean = false, // dpi-c l2tlb debug only 305 softPTWDelay: Int = 1 306){ 307 def vlWidth = log2Up(VLEN) + 1 308 309 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 310 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 311 312 val intSchdParams = { 313 implicit val schdType: SchedulerType = IntScheduler() 314 SchdBlockParams(Seq( 315 IssueBlockParams(Seq( 316 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 317 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 318 ), numEntries = IssueQueueSize, numEnq = 2), 319 IssueBlockParams(Seq( 320 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 321 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 322 ), numEntries = IssueQueueSize, numEnq = 2), 323 IssueBlockParams(Seq( 324 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 325 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 326 ), numEntries = IssueQueueSize, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 329 ), numEntries = IssueQueueSize, numEnq = 2), 330 IssueBlockParams(Seq( 331 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 332 ), numEntries = IssueQueueSize, numEnq = 2), 333 ), 334 numPregs = intPreg.numEntries, 335 numDeqOutside = 0, 336 schdType = schdType, 337 rfDataWidth = intPreg.dataCfg.dataWidth, 338 numUopIn = dpParams.IntDqDeqWidth, 339 ) 340 } 341 val vfSchdParams = { 342 implicit val schdType: SchedulerType = VfScheduler() 343 SchdBlockParams(Seq( 344 IssueBlockParams(Seq( 345 ExeUnitParams("FEX0", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(12, 0)), Seq(VfRD(13, 0)))), 346 ), numEntries = IssueQueueSize, numEnq = 2), 347 IssueBlockParams(Seq( 348 ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 349 ), numEntries = IssueQueueSize, numEnq = 2), 350 IssueBlockParams(Seq( 351 ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 2, 0), IntWB(port = 9, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 352 ExeUnitParams("VEX2", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 3, 0), IntWB(port = 5, 1)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 353 ), numEntries = IssueQueueSize, numEnq = 2), 354 IssueBlockParams(Seq( 355 ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 356 ), numEntries = IssueQueueSize, numEnq = 2), 357 ), 358 numPregs = vfPreg.numEntries, 359 numDeqOutside = 0, 360 schdType = schdType, 361 rfDataWidth = vfPreg.dataCfg.dataWidth, 362 numUopIn = dpParams.FpDqDeqWidth, 363 ) 364 } 365 366 val memSchdParams = { 367 implicit val schdType: SchedulerType = MemScheduler() 368 val rfDataWidth = 64 369 370 SchdBlockParams(Seq( 371 IssueBlockParams(Seq( 372 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 373 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 374 ), numEntries = IssueQueueSize, numEnq = 2), 375 IssueBlockParams(Seq( 376 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))), 377 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))), 378 ), numEntries = IssueQueueSize, numEnq = 2), 379 IssueBlockParams(Seq( 380 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 381 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 382 ), numEntries = IssueQueueSize, numEnq = 2), 383 IssueBlockParams(Seq( 384 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 385 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 386 ), numEntries = IssueQueueSize, numEnq = 2), 387 ), 388 numPregs = intPreg.numEntries max vfPreg.numEntries, 389 numDeqOutside = 0, 390 schdType = schdType, 391 rfDataWidth = rfDataWidth, 392 numUopIn = dpParams.LsDqDeqWidth, 393 ) 394 } 395 396 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 397 398 def iqWakeUpParams = { 399 Seq( 400 WakeUpConfig("ALU0" -> "ALU0"), 401 WakeUpConfig("ALU0" -> "ALU1"), 402 WakeUpConfig("ALU0" -> "MUL0"), 403 WakeUpConfig("ALU0" -> "MUL1"), 404 WakeUpConfig("ALU1" -> "ALU0"), 405 WakeUpConfig("ALU1" -> "ALU1"), 406 WakeUpConfig("ALU0" -> "BJU0"), 407 WakeUpConfig("ALU0" -> "BJU1"), 408 WakeUpConfig("ALU1" -> "BJU0"), 409 WakeUpConfig("ALU1" -> "BJU1"), 410 WakeUpConfig("ALU0" -> "LDU0"), 411 WakeUpConfig("ALU0" -> "LDU1"), 412 WakeUpConfig("ALU1" -> "LDU0"), 413 WakeUpConfig("ALU1" -> "LDU1"), 414 WakeUpConfig("ALU0" -> "STA0"), 415 WakeUpConfig("ALU0" -> "STA1"), 416 WakeUpConfig("ALU1" -> "STA0"), 417 WakeUpConfig("ALU1" -> "STA1"), 418 WakeUpConfig("MUL0" -> "ALU0"), 419 WakeUpConfig("MUL0" -> "ALU1"), 420 WakeUpConfig("MUL0" -> "MUL0"), 421 WakeUpConfig("MUL0" -> "MUL1"), 422 WakeUpConfig("MUL1" -> "ALU0"), 423 WakeUpConfig("MUL1" -> "ALU1"), 424 WakeUpConfig("MUL0" -> "BJU0"), 425 WakeUpConfig("MUL0" -> "BJU1"), 426 WakeUpConfig("MUL1" -> "BJU0"), 427 WakeUpConfig("MUL1" -> "BJU1"), 428 WakeUpConfig("MUL0" -> "LDU0"), 429 WakeUpConfig("MUL0" -> "LDU1"), 430 WakeUpConfig("MUL1" -> "LDU0"), 431 WakeUpConfig("MUL1" -> "LDU1"), 432 WakeUpConfig("MUL0" -> "STA0"), 433 WakeUpConfig("MUL0" -> "STA1"), 434 WakeUpConfig("MUL1" -> "STA0"), 435 WakeUpConfig("MUL1" -> "STA1"), 436 WakeUpConfig("IMISC0" -> "FEX0"), 437 ) 438 } 439 440 def backendParams: BackendParams = backend.BackendParams( 441 Map( 442 IntScheduler() -> intSchdParams, 443 VfScheduler() -> vfSchdParams, 444 MemScheduler() -> memSchdParams, 445 ), 446 Seq( 447 intPreg, 448 vfPreg, 449 ), 450 iqWakeUpParams, 451 ) 452} 453 454case object DebugOptionsKey extends Field[DebugOptions] 455 456case class DebugOptions 457( 458 FPGAPlatform: Boolean = false, 459 EnableDifftest: Boolean = false, 460 AlwaysBasicDiff: Boolean = true, 461 EnableDebug: Boolean = false, 462 EnablePerfDebug: Boolean = true, 463 UseDRAMSim: Boolean = false, 464 EnableConstantin: Boolean = false, 465 EnableChiselDB: Boolean = false, 466 AlwaysBasicDB: Boolean = true, 467 EnableTopDown: Boolean = false, 468) 469 470trait HasXSParameter { 471 472 implicit val p: Parameters 473 474 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 475 476 val coreParams = p(XSCoreParamsKey) 477 val env = p(DebugOptionsKey) 478 479 val XLEN = coreParams.XLEN 480 val VLEN = coreParams.VLEN 481 val ELEN = coreParams.ELEN 482 val minFLen = 32 483 val fLen = 64 484 def xLen = XLEN 485 486 val HasMExtension = coreParams.HasMExtension 487 val HasCExtension = coreParams.HasCExtension 488 val HasDiv = coreParams.HasDiv 489 val HasIcache = coreParams.HasICache 490 val HasDcache = coreParams.HasDCache 491 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 492 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 493 val AsidLength = coreParams.AsidLength 494 val ReSelectLen = coreParams.ReSelectLen 495 val AddrBytes = AddrBits / 8 // unused 496 val DataBits = XLEN 497 val DataBytes = DataBits / 8 498 val VDataBytes = VLEN / 8 499 val HasFPU = coreParams.HasFPU 500 val HasVPU = coreParams.HasVPU 501 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 502 val FetchWidth = coreParams.FetchWidth 503 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 504 val EnableBPU = coreParams.EnableBPU 505 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 506 val EnableRAS = coreParams.EnableRAS 507 val EnableLB = coreParams.EnableLB 508 val EnableLoop = coreParams.EnableLoop 509 val EnableSC = coreParams.EnableSC 510 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 511 val HistoryLength = coreParams.HistoryLength 512 val EnableGHistDiff = coreParams.EnableGHistDiff 513 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 514 val UbtbGHRLength = coreParams.UbtbGHRLength 515 val UbtbSize = coreParams.UbtbSize 516 val EnableFauFTB = coreParams.EnableFauFTB 517 val FtbSize = coreParams.FtbSize 518 val FtbWays = coreParams.FtbWays 519 val RasSize = coreParams.RasSize 520 521 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 522 coreParams.branchPredictor(resp_in, p) 523 } 524 val numBr = coreParams.numBr 525 val TageTableInfos = coreParams.TageTableInfos 526 val TageBanks = coreParams.numBr 527 val SCNRows = coreParams.SCNRows 528 val SCCtrBits = coreParams.SCCtrBits 529 val SCHistLens = coreParams.SCHistLens 530 val SCNTables = coreParams.SCNTables 531 532 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 533 case ((n, cb), h) => (n, cb, h) 534 } 535 val ITTageTableInfos = coreParams.ITTageTableInfos 536 type FoldedHistoryInfo = Tuple2[Int, Int] 537 val foldedGHistInfos = 538 (TageTableInfos.map{ case (nRows, h, t) => 539 if (h > 0) 540 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 541 else 542 Set[FoldedHistoryInfo]() 543 }.reduce(_++_).toSet ++ 544 SCTableInfos.map{ case (nRows, _, h) => 545 if (h > 0) 546 Set((h, min(log2Ceil(nRows/TageBanks), h))) 547 else 548 Set[FoldedHistoryInfo]() 549 }.reduce(_++_).toSet ++ 550 ITTageTableInfos.map{ case (nRows, h, t) => 551 if (h > 0) 552 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 553 else 554 Set[FoldedHistoryInfo]() 555 }.reduce(_++_) ++ 556 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 557 ).toList 558 559 560 561 val CacheLineSize = coreParams.CacheLineSize 562 val CacheLineHalfWord = CacheLineSize / 16 563 val ExtHistoryLength = HistoryLength + 64 564 val IBufSize = coreParams.IBufSize 565 val DecodeWidth = coreParams.DecodeWidth 566 val RenameWidth = coreParams.RenameWidth 567 val CommitWidth = coreParams.CommitWidth 568 val MaxUopSize = coreParams.MaxUopSize 569 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 570 val RenameSnapshotNum = coreParams.RenameSnapshotNum 571 val FtqSize = coreParams.FtqSize 572 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 573 val IntLogicRegs = coreParams.IntLogicRegs 574 val FpLogicRegs = coreParams.FpLogicRegs 575 val VecLogicRegs = coreParams.VecLogicRegs 576 val VCONFIG_IDX = coreParams.VCONFIG_IDX 577 val IntPhyRegs = coreParams.intPreg.numEntries 578 val VfPhyRegs = coreParams.vfPreg.numEntries 579 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 580 val RobSize = coreParams.RobSize 581 val RabSize = coreParams.RabSize 582 val IntRefCounterWidth = log2Ceil(RobSize) 583 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 584 val LoadQueueRARSize = coreParams.LoadQueueRARSize 585 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 586 val RollbackGroupSize = coreParams.RollbackGroupSize 587 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 588 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 589 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 590 val StoreQueueSize = coreParams.StoreQueueSize 591 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 592 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 593 val VlsQueueSize = coreParams.VlsQueueSize 594 val dpParams = coreParams.dpParams 595 596 def backendParams: BackendParams = coreParams.backendParams 597 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 598 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 599 val LoadPipelineWidth = coreParams.LoadPipelineWidth 600 val StorePipelineWidth = coreParams.StorePipelineWidth 601 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 602 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 603 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 604 val StoreBufferSize = coreParams.StoreBufferSize 605 val StoreBufferThreshold = coreParams.StoreBufferThreshold 606 val EnsbufferWidth = coreParams.EnsbufferWidth 607 val UncacheBufferSize = coreParams.UncacheBufferSize 608 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 609 val EnableFastForward = coreParams.EnableFastForward 610 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 611 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 612 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 613 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 614 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 615 val asidLen = coreParams.MMUAsidLen 616 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 617 val refillBothTlb = coreParams.refillBothTlb 618 val iwpuParam = coreParams.iwpuParameters 619 val dwpuParam = coreParams.dwpuParameters 620 val itlbParams = coreParams.itlbParameters 621 val ldtlbParams = coreParams.ldtlbParameters 622 val sttlbParams = coreParams.sttlbParameters 623 val pftlbParams = coreParams.pftlbParameters 624 val btlbParams = coreParams.btlbParameters 625 val l2tlbParams = coreParams.l2tlbParameters 626 val NumPerfCounters = coreParams.NumPerfCounters 627 628 val instBytes = if (HasCExtension) 2 else 4 629 val instOffsetBits = log2Ceil(instBytes) 630 631 val icacheParameters = coreParams.icacheParameters 632 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 633 634 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 635 // for constrained LR/SC loop 636 val LRSCCycles = 64 637 // for lr storm 638 val LRSCBackOff = 8 639 640 // cache hierarchy configurations 641 val l1BusDataWidth = 256 642 643 // load violation predict 644 val ResetTimeMax2Pow = 20 //1078576 645 val ResetTimeMin2Pow = 10 //1024 646 // wait table parameters 647 val WaitTableSize = 1024 648 val MemPredPCWidth = log2Up(WaitTableSize) 649 val LWTUse2BitCounter = true 650 // store set parameters 651 val SSITSize = WaitTableSize 652 val LFSTSize = 32 653 val SSIDWidth = log2Up(LFSTSize) 654 val LFSTWidth = 4 655 val StoreSetEnable = true // LWT will be disabled if SS is enabled 656 val LFSTEnable = false 657 658 val PCntIncrStep: Int = 6 659 val numPCntHc: Int = 25 660 val numPCntPtw: Int = 19 661 662 val numCSRPCntFrontend = 8 663 val numCSRPCntCtrl = 8 664 val numCSRPCntLsu = 8 665 val numCSRPCntHc = 5 666} 667