1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 HasCustomCSRCacheOp: Boolean = true, 48 FetchWidth: Int = 8, 49 AsidLength: Int = 16, 50 EnableBPU: Boolean = true, 51 EnableBPD: Boolean = true, 52 EnableRAS: Boolean = true, 53 EnableLB: Boolean = false, 54 EnableLoop: Boolean = true, 55 EnableSC: Boolean = true, 56 EnbaleTlbDebug: Boolean = false, 57 EnableJal: Boolean = false, 58 EnableUBTB: Boolean = true, 59 HistoryLength: Int = 64, 60 PathHistoryLength: Int = 16, 61 BtbSize: Int = 2048, 62 JbtacSize: Int = 1024, 63 JbtacBanks: Int = 8, 64 RasSize: Int = 32, 65 CacheLineSize: Int = 512, 66 UBtbWays: Int = 16, 67 BtbWays: Int = 2, 68 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 69 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 70 // val loop = Module(new LoopPredictor) 71 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 72 // else Module(new Tage) } 73 // else { Module(new FakeTage) }) 74 val ftb = Module(new FTB()(p)) 75 val ubtb = Module(new MicroBTB()(p)) 76 val bim = Module(new BIM()(p)) 77 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 78 val ras = Module(new RAS()(p)) 79 val ittage = Module(new ITTage()(p)) 80 // val tage = Module(new Tage()(p)) 81 // val fake = Module(new FakePredictor()(p)) 82 83 // val preds = Seq(loop, tage, btb, ubtb, bim) 84 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 85 preds.map(_.io := DontCare) 86 87 // ubtb.io.resp_in(0) := resp_in 88 // bim.io.resp_in(0) := ubtb.io.resp 89 // btb.io.resp_in(0) := bim.io.resp 90 // tage.io.resp_in(0) := btb.io.resp 91 // loop.io.resp_in(0) := tage.io.resp 92 bim.io.in.bits.resp_in(0) := resp_in 93 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 94 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 95 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 96 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 97 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 98 99 (preds, ras.io.out.resp) 100 }), 101 IBufSize: Int = 48, 102 DecodeWidth: Int = 6, 103 RenameWidth: Int = 6, 104 CommitWidth: Int = 6, 105 FtqSize: Int = 64, 106 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 107 IssQueSize: Int = 16, 108 NRPhyRegs: Int = 192, 109 NRIntReadPorts: Int = 14, 110 NRIntWritePorts: Int = 8, 111 NRFpReadPorts: Int = 14, 112 NRFpWritePorts: Int = 8, 113 LoadQueueSize: Int = 80, 114 StoreQueueSize: Int = 64, 115 RobSize: Int = 256, 116 dpParams: DispatchParameters = DispatchParameters( 117 IntDqSize = 16, 118 FpDqSize = 16, 119 LsDqSize = 16, 120 IntDqDeqWidth = 4, 121 FpDqDeqWidth = 4, 122 LsDqDeqWidth = 4 123 ), 124 exuParameters: ExuParameters = ExuParameters( 125 JmpCnt = 1, 126 AluCnt = 4, 127 MulCnt = 0, 128 MduCnt = 2, 129 FmacCnt = 4, 130 FmiscCnt = 2, 131 FmiscDivSqrtCnt = 0, 132 LduCnt = 2, 133 StuCnt = 2 134 ), 135 LoadPipelineWidth: Int = 2, 136 StorePipelineWidth: Int = 2, 137 StoreBufferSize: Int = 16, 138 StoreBufferThreshold: Int = 7, 139 EnableFastForward: Boolean = true, 140 RefillSize: Int = 512, 141 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 142 itlbParameters: TLBParameters = TLBParameters( 143 name = "itlb", 144 fetchi = true, 145 useDmode = false, 146 sameCycle = true, 147 normalNWays = 32, 148 normalReplacer = Some("plru"), 149 superNWays = 4, 150 superReplacer = Some("plru"), 151 shouldBlock = true 152 ), 153 ldtlbParameters: TLBParameters = TLBParameters( 154 name = "ldtlb", 155 normalNSets = 128, 156 normalNWays = 1, 157 normalAssociative = "sa", 158 normalReplacer = Some("setplru"), 159 superNWays = 8, 160 normalAsVictim = true, 161 outReplace = true 162 ), 163 sttlbParameters: TLBParameters = TLBParameters( 164 name = "sttlb", 165 normalNSets = 128, 166 normalNWays = 1, 167 normalAssociative = "sa", 168 normalReplacer = Some("setplru"), 169 superNWays = 8, 170 normalAsVictim = true, 171 outReplace = true 172 ), 173 refillBothTlb: Boolean = false, 174 btlbParameters: TLBParameters = TLBParameters( 175 name = "btlb", 176 normalNSets = 1, 177 normalNWays = 64, 178 superNWays = 4, 179 ), 180 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 181 NumPMP: Int = 16, // 0 or 16 or 64 182 NumPerfCounters: Int = 16, 183 icacheParameters: ICacheParameters = ICacheParameters( 184 tagECC = Some("parity"), 185 dataECC = Some("parity"), 186 replacer = Some("setplru"), 187 nMissEntries = 2 188 ), 189 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 190 tagECC = Some("secded"), 191 dataECC = Some("secded"), 192 replacer = Some("setplru"), 193 nMissEntries = 16, 194 nProbeEntries = 16, 195 nReleaseEntries = 32 196 )), 197 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 198 name = "l2", 199 level = 2, 200 ways = 8, 201 sets = 1024, // default 512KB L2 202 prefetch = Some(huancun.prefetch.BOPParameters()) 203 )), 204 L2NBanks: Int = 1, 205 usePTWRepeater: Boolean = false, 206 softPTW: Boolean = false // dpi-c debug only 207){ 208 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 209 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 210 211 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 212 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 213 214 val fpExuConfigs = 215 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 216 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 217 218 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 219} 220 221case object DebugOptionsKey extends Field[DebugOptions] 222 223case class DebugOptions 224( 225 FPGAPlatform: Boolean = true, 226 EnableDebug: Boolean = true, 227 EnablePerfDebug: Boolean = true, 228 UseDRAMSim: Boolean = false 229) 230 231trait HasXSParameter { 232 233 implicit val p: Parameters 234 235 val coreParams = p(XSCoreParamsKey) 236 val env = p(DebugOptionsKey) 237 238 val XLEN = coreParams.XLEN 239 val hardId = coreParams.HartId 240 val minFLen = 32 241 val fLen = 64 242 def xLen = XLEN 243 244 val HasMExtension = coreParams.HasMExtension 245 val HasCExtension = coreParams.HasCExtension 246 val HasDiv = coreParams.HasDiv 247 val HasIcache = coreParams.HasICache 248 val HasDcache = coreParams.HasDCache 249 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 250 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 251 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 252 val AsidLength = coreParams.AsidLength 253 val AddrBytes = AddrBits / 8 // unused 254 val DataBits = XLEN 255 val DataBytes = DataBits / 8 256 val HasFPU = coreParams.HasFPU 257 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 258 val FetchWidth = coreParams.FetchWidth 259 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 260 val EnableBPU = coreParams.EnableBPU 261 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 262 val EnableRAS = coreParams.EnableRAS 263 val EnableLB = coreParams.EnableLB 264 val EnableLoop = coreParams.EnableLoop 265 val EnableSC = coreParams.EnableSC 266 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 267 val HistoryLength = coreParams.HistoryLength 268 val PathHistoryLength = coreParams.PathHistoryLength 269 val BtbSize = coreParams.BtbSize 270 // val BtbWays = 4 271 val BtbBanks = PredictWidth 272 // val BtbSets = BtbSize / BtbWays 273 val JbtacSize = coreParams.JbtacSize 274 val JbtacBanks = coreParams.JbtacBanks 275 val RasSize = coreParams.RasSize 276 277 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 278 coreParams.branchPredictor(resp_in, p, enableSC) 279 } 280 281 val CacheLineSize = coreParams.CacheLineSize 282 val CacheLineHalfWord = CacheLineSize / 16 283 val ExtHistoryLength = HistoryLength + 64 284 val UBtbWays = coreParams.UBtbWays 285 val BtbWays = coreParams.BtbWays 286 val IBufSize = coreParams.IBufSize 287 val DecodeWidth = coreParams.DecodeWidth 288 val RenameWidth = coreParams.RenameWidth 289 val CommitWidth = coreParams.CommitWidth 290 val FtqSize = coreParams.FtqSize 291 val IssQueSize = coreParams.IssQueSize 292 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 293 val NRPhyRegs = coreParams.NRPhyRegs 294 val PhyRegIdxWidth = log2Up(NRPhyRegs) 295 val RobSize = coreParams.RobSize 296 val IntRefCounterWidth = log2Ceil(RobSize) 297 val StdFreeListSize = NRPhyRegs - 32 298 val MEFreeListSize = NRPhyRegs 299 val LoadQueueSize = coreParams.LoadQueueSize 300 val StoreQueueSize = coreParams.StoreQueueSize 301 val dpParams = coreParams.dpParams 302 val exuParameters = coreParams.exuParameters 303 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 304 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 305 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 306 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 307 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 308 val LoadPipelineWidth = coreParams.LoadPipelineWidth 309 val StorePipelineWidth = coreParams.StorePipelineWidth 310 val StoreBufferSize = coreParams.StoreBufferSize 311 val StoreBufferThreshold = coreParams.StoreBufferThreshold 312 val EnableFastForward = coreParams.EnableFastForward 313 val RefillSize = coreParams.RefillSize 314 val asidLen = coreParams.MMUAsidLen 315 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 316 val refillBothTlb = coreParams.refillBothTlb 317 val itlbParams = coreParams.itlbParameters 318 val ldtlbParams = coreParams.ldtlbParameters 319 val sttlbParams = coreParams.sttlbParameters 320 val btlbParams = coreParams.btlbParameters 321 val l2tlbParams = coreParams.l2tlbParameters 322 val NumPMP = coreParams.NumPMP 323 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 324 val NumPerfCounters = coreParams.NumPerfCounters 325 326 val instBytes = if (HasCExtension) 2 else 4 327 val instOffsetBits = log2Ceil(instBytes) 328 329 val icacheParameters = coreParams.icacheParameters 330 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 331 332 val LRSCCycles = 100 333 334 // cache hierarchy configurations 335 val l1BusDataWidth = 256 336 337 // load violation predict 338 val ResetTimeMax2Pow = 20 //1078576 339 val ResetTimeMin2Pow = 10 //1024 340 // wait table parameters 341 val WaitTableSize = 1024 342 val MemPredPCWidth = log2Up(WaitTableSize) 343 val LWTUse2BitCounter = true 344 // store set parameters 345 val SSITSize = WaitTableSize 346 val LFSTSize = 32 347 val SSIDWidth = log2Up(LFSTSize) 348 val LFSTWidth = 4 349 val StoreSetEnable = true // LWT will be disabled if SS is enabled 350 351 val loadExuConfigs = coreParams.loadExuConfigs 352 val storeExuConfigs = coreParams.storeExuConfigs 353 354 val intExuConfigs = coreParams.intExuConfigs 355 356 val fpExuConfigs = coreParams.fpExuConfigs 357 358 val exuConfigs = coreParams.exuConfigs 359 360} 361