1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.cache.wpu.WPUParameters 34import coupledL2._ 35import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 36 37import scala.math.min 38 39case object XSTileKey extends Field[Seq[XSCoreParameters]] 40 41case object XSCoreParamsKey extends Field[XSCoreParameters] 42 43case class XSCoreParameters 44( 45 HasPrefetch: Boolean = false, 46 HartId: Int = 0, 47 XLEN: Int = 64, 48 VLEN: Int = 128, 49 HasMExtension: Boolean = true, 50 HasCExtension: Boolean = true, 51 HasDiv: Boolean = true, 52 HasICache: Boolean = true, 53 HasDCache: Boolean = true, 54 AddrBits: Int = 64, 55 VAddrBits: Int = 39, 56 HasFPU: Boolean = true, 57 HasCustomCSRCacheOp: Boolean = true, 58 FetchWidth: Int = 8, 59 AsidLength: Int = 16, 60 EnableBPU: Boolean = true, 61 EnableBPD: Boolean = true, 62 EnableRAS: Boolean = true, 63 EnableLB: Boolean = false, 64 EnableLoop: Boolean = true, 65 EnableSC: Boolean = true, 66 EnbaleTlbDebug: Boolean = false, 67 EnableJal: Boolean = false, 68 EnableFauFTB: Boolean = true, 69 UbtbGHRLength: Int = 4, 70 // HistoryLength: Int = 512, 71 EnableGHistDiff: Boolean = true, 72 EnableCommitGHistDiff: Boolean = true, 73 UbtbSize: Int = 256, 74 FtbSize: Int = 2048, 75 RasSize: Int = 16, 76 RasSpecSize: Int = 32, 77 RasCtrSize: Int = 3, 78 CacheLineSize: Int = 512, 79 FtbWays: Int = 4, 80 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 81 // Sets Hist Tag 82 // Seq(( 2048, 2, 8), 83 // ( 2048, 9, 8), 84 // ( 2048, 13, 8), 85 // ( 2048, 20, 8), 86 // ( 2048, 26, 8), 87 // ( 2048, 44, 8), 88 // ( 2048, 73, 8), 89 // ( 2048, 256, 8)), 90 Seq(( 4096, 8, 8), 91 ( 4096, 13, 8), 92 ( 4096, 32, 8), 93 ( 4096, 119, 8)), 94 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 Seq(( 256, 4, 9), 97 ( 256, 8, 9), 98 ( 512, 13, 9), 99 ( 512, 16, 9), 100 ( 512, 32, 9)), 101 SCNRows: Int = 512, 102 SCNTables: Int = 4, 103 SCCtrBits: Int = 6, 104 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 105 numBr: Int = 2, 106 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 107 ((resp_in: BranchPredictionResp, p: Parameters) => { 108 val ftb = Module(new FTB()(p)) 109 val ubtb =Module(new FauFTB()(p)) 110 // val bim = Module(new BIM()(p)) 111 val tage = Module(new Tage_SC()(p)) 112 val ras = Module(new RAS()(p)) 113 val ittage = Module(new ITTage()(p)) 114 val preds = Seq(ubtb, tage, ftb, ittage, ras) 115 preds.map(_.io := DontCare) 116 117 // ubtb.io.resp_in(0) := resp_in 118 // bim.io.resp_in(0) := ubtb.io.resp 119 // btb.io.resp_in(0) := bim.io.resp 120 // tage.io.resp_in(0) := btb.io.resp 121 // loop.io.resp_in(0) := tage.io.resp 122 ubtb.io.in.bits.resp_in(0) := resp_in 123 tage.io.in.bits.resp_in(0) := ubtb.io.out 124 ftb.io.in.bits.resp_in(0) := tage.io.out 125 ittage.io.in.bits.resp_in(0) := ftb.io.out 126 ras.io.in.bits.resp_in(0) := ittage.io.out 127 128 (preds, ras.io.out) 129 }), 130 ICacheECCForceError: Boolean = false, 131 IBufSize: Int = 48, 132 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 133 DecodeWidth: Int = 6, 134 RenameWidth: Int = 6, 135 CommitWidth: Int = 6, 136 EnableRenameSnapshot: Boolean = true, 137 RenameSnapshotNum: Int = 4, 138 FtqSize: Int = 64, 139 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 140 IssQueSize: Int = 16, 141 NRPhyRegs: Int = 192, 142 VirtualLoadQueueSize: Int = 80, 143 LoadQueueRARSize: Int = 80, 144 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 145 RollbackGroupSize: Int = 8, 146 LoadQueueReplaySize: Int = 72, 147 LoadUncacheBufferSize: Int = 20, 148 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 149 StoreQueueSize: Int = 64, 150 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 151 StoreQueueForwardWithMask: Boolean = true, 152 VlsQueueSize: Int = 8, 153 RobSize: Int = 256, 154 dpParams: DispatchParameters = DispatchParameters( 155 IntDqSize = 16, 156 FpDqSize = 16, 157 LsDqSize = 16, 158 IntDqDeqWidth = 4, 159 FpDqDeqWidth = 4, 160 LsDqDeqWidth = 4 161 ), 162 exuParameters: ExuParameters = ExuParameters( 163 JmpCnt = 1, 164 AluCnt = 4, 165 MulCnt = 0, 166 MduCnt = 2, 167 FmacCnt = 4, 168 FmiscCnt = 2, 169 FmiscDivSqrtCnt = 0, 170 LduCnt = 2, 171 StuCnt = 2 172 ), 173 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 174 LoadPipelineWidth: Int = 2, 175 StorePipelineWidth: Int = 2, 176 VecMemSrcInWidth: Int = 2, 177 VecMemInstWbWidth: Int = 1, 178 VecMemDispatchWidth: Int = 1, 179 StoreBufferSize: Int = 16, 180 StoreBufferThreshold: Int = 7, 181 EnsbufferWidth: Int = 2, 182 UncacheBufferSize: Int = 4, 183 EnableLoadToLoadForward: Boolean = false, 184 EnableFastForward: Boolean = true, 185 EnableLdVioCheckAfterReset: Boolean = true, 186 EnableSoftPrefetchAfterReset: Boolean = true, 187 EnableCacheErrorAfterReset: Boolean = true, 188 EnableAccurateLoadError: Boolean = true, 189 EnableUncacheWriteOutstanding: Boolean = false, 190 EnableStorePrefetchAtIssue: Boolean = false, 191 EnableStorePrefetchAtCommit: Boolean = false, 192 EnableAtCommitMissTrigger: Boolean = true, 193 EnableStorePrefetchSMS: Boolean = false, 194 EnableStorePrefetchSPB: Boolean = false, 195 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 196 ReSelectLen: Int = 7, // load replay queue replay select counter len 197 iwpuParameters: WPUParameters = WPUParameters( 198 enWPU = false, 199 algoName = "mmru", 200 isICache = true, 201 ), 202 dwpuParameters: WPUParameters = WPUParameters( 203 enWPU = false, 204 algoName = "mmru", 205 enCfPred = false, 206 isICache = false, 207 ), 208 itlbParameters: TLBParameters = TLBParameters( 209 name = "itlb", 210 fetchi = true, 211 useDmode = false, 212 NWays = 48, 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 NWays = 48, 219 outReplace = false, 220 partialStaticPMP = true, 221 outsideRecvFlush = true, 222 saveLevel = true 223 ), 224 sttlbParameters: TLBParameters = TLBParameters( 225 name = "sttlb", 226 NWays = 48, 227 outReplace = false, 228 partialStaticPMP = true, 229 outsideRecvFlush = true, 230 saveLevel = true 231 ), 232 pftlbParameters: TLBParameters = TLBParameters( 233 name = "pftlb", 234 NWays = 48, 235 outReplace = false, 236 partialStaticPMP = true, 237 outsideRecvFlush = true, 238 saveLevel = true 239 ), 240 refillBothTlb: Boolean = false, 241 btlbParameters: TLBParameters = TLBParameters( 242 name = "btlb", 243 NWays = 48, 244 ), 245 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 246 NumPerfCounters: Int = 16, 247 icacheParameters: ICacheParameters = ICacheParameters( 248 tagECC = Some("parity"), 249 dataECC = Some("parity"), 250 replacer = Some("setplru"), 251 nMissEntries = 2, 252 nProbeEntries = 2, 253 nPrefetchEntries = 12, 254 nPrefBufferEntries = 32, 255 ), 256 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 257 tagECC = Some("secded"), 258 dataECC = Some("secded"), 259 replacer = Some("setplru"), 260 nMissEntries = 16, 261 nProbeEntries = 8, 262 nReleaseEntries = 18, 263 nMaxPrefetchEntry = 6, 264 )), 265 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 266 name = "l2", 267 ways = 8, 268 sets = 1024, // default 512KB L2 269 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 270 )), 271 L2NBanks: Int = 1, 272 usePTWRepeater: Boolean = false, 273 softTLB: Boolean = false, // dpi-c l1tlb debug only 274 softPTW: Boolean = false, // dpi-c l2tlb debug only 275 softPTWDelay: Int = 1 276){ 277 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 278 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 279 280 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 281 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 282 283 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 284 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 285 286 val fpExuConfigs = 287 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 288 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 289 290 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 291} 292 293case object DebugOptionsKey extends Field[DebugOptions] 294 295case class DebugOptions 296( 297 FPGAPlatform: Boolean = false, 298 EnableDifftest: Boolean = false, 299 AlwaysBasicDiff: Boolean = true, 300 EnableDebug: Boolean = false, 301 EnablePerfDebug: Boolean = true, 302 UseDRAMSim: Boolean = false, 303 EnableConstantin: Boolean = false, 304 EnableChiselDB: Boolean = false, 305 AlwaysBasicDB: Boolean = true, 306 EnableRollingDB: Boolean = false 307) 308 309trait HasXSParameter { 310 311 implicit val p: Parameters 312 313 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 314 315 val coreParams = p(XSCoreParamsKey) 316 val env = p(DebugOptionsKey) 317 318 val XLEN = coreParams.XLEN 319 val VLEN = coreParams.VLEN 320 val minFLen = 32 321 val fLen = 64 322 def xLen = XLEN 323 324 val HasMExtension = coreParams.HasMExtension 325 val HasCExtension = coreParams.HasCExtension 326 val HasDiv = coreParams.HasDiv 327 val HasIcache = coreParams.HasICache 328 val HasDcache = coreParams.HasDCache 329 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 330 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 331 val AsidLength = coreParams.AsidLength 332 val ReSelectLen = coreParams.ReSelectLen 333 val AddrBytes = AddrBits / 8 // unused 334 val DataBits = XLEN 335 val DataBytes = DataBits / 8 336 val VDataBytes = VLEN / 8 337 val HasFPU = coreParams.HasFPU 338 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 339 val FetchWidth = coreParams.FetchWidth 340 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 341 val EnableBPU = coreParams.EnableBPU 342 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 343 val EnableRAS = coreParams.EnableRAS 344 val EnableLB = coreParams.EnableLB 345 val EnableLoop = coreParams.EnableLoop 346 val EnableSC = coreParams.EnableSC 347 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 348 val HistoryLength = coreParams.HistoryLength 349 val EnableGHistDiff = coreParams.EnableGHistDiff 350 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 351 val UbtbGHRLength = coreParams.UbtbGHRLength 352 val UbtbSize = coreParams.UbtbSize 353 val EnableFauFTB = coreParams.EnableFauFTB 354 val FtbSize = coreParams.FtbSize 355 val FtbWays = coreParams.FtbWays 356 val RasSize = coreParams.RasSize 357 val RasSpecSize = coreParams.RasSpecSize 358 val RasCtrSize = coreParams.RasCtrSize 359 360 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 361 coreParams.branchPredictor(resp_in, p) 362 } 363 val numBr = coreParams.numBr 364 val TageTableInfos = coreParams.TageTableInfos 365 val TageBanks = coreParams.numBr 366 val SCNRows = coreParams.SCNRows 367 val SCCtrBits = coreParams.SCCtrBits 368 val SCHistLens = coreParams.SCHistLens 369 val SCNTables = coreParams.SCNTables 370 371 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 372 case ((n, cb), h) => (n, cb, h) 373 } 374 val ITTageTableInfos = coreParams.ITTageTableInfos 375 type FoldedHistoryInfo = Tuple2[Int, Int] 376 val foldedGHistInfos = 377 (TageTableInfos.map{ case (nRows, h, t) => 378 if (h > 0) 379 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 380 else 381 Set[FoldedHistoryInfo]() 382 }.reduce(_++_).toSet ++ 383 SCTableInfos.map{ case (nRows, _, h) => 384 if (h > 0) 385 Set((h, min(log2Ceil(nRows/TageBanks), h))) 386 else 387 Set[FoldedHistoryInfo]() 388 }.reduce(_++_).toSet ++ 389 ITTageTableInfos.map{ case (nRows, h, t) => 390 if (h > 0) 391 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 392 else 393 Set[FoldedHistoryInfo]() 394 }.reduce(_++_) ++ 395 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 396 ).toList 397 398 399 400 val CacheLineSize = coreParams.CacheLineSize 401 val CacheLineHalfWord = CacheLineSize / 16 402 val ExtHistoryLength = HistoryLength + 64 403 val ICacheECCForceError = coreParams.ICacheECCForceError 404 val IBufSize = coreParams.IBufSize 405 val IBufNBank = coreParams.IBufNBank 406 val DecodeWidth = coreParams.DecodeWidth 407 val RenameWidth = coreParams.RenameWidth 408 val CommitWidth = coreParams.CommitWidth 409 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 410 val RenameSnapshotNum = coreParams.RenameSnapshotNum 411 val FtqSize = coreParams.FtqSize 412 val IssQueSize = coreParams.IssQueSize 413 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 414 val NRPhyRegs = coreParams.NRPhyRegs 415 val PhyRegIdxWidth = log2Up(NRPhyRegs) 416 val RobSize = coreParams.RobSize 417 val IntRefCounterWidth = log2Ceil(RobSize) 418 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 419 val LoadQueueRARSize = coreParams.LoadQueueRARSize 420 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 421 val RollbackGroupSize = coreParams.RollbackGroupSize 422 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 423 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 424 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 425 val StoreQueueSize = coreParams.StoreQueueSize 426 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 427 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 428 val VlsQueueSize = coreParams.VlsQueueSize 429 val dpParams = coreParams.dpParams 430 val exuParameters = coreParams.exuParameters 431 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 432 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 433 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 434 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 435 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 436 val NumRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 437 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 438 val FtqRedirectAheadNum = exuParameters.AluCnt 439 val LoadPipelineWidth = coreParams.LoadPipelineWidth 440 val StorePipelineWidth = coreParams.StorePipelineWidth 441 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 442 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 443 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 444 val StoreBufferSize = coreParams.StoreBufferSize 445 val StoreBufferThreshold = coreParams.StoreBufferThreshold 446 val EnsbufferWidth = coreParams.EnsbufferWidth 447 val UncacheBufferSize = coreParams.UncacheBufferSize 448 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 449 val EnableFastForward = coreParams.EnableFastForward 450 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 451 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 452 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 453 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 454 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 455 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 456 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 457 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 458 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 459 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 460 require(LoadPipelineWidth == StorePipelineWidth, "LoadPipelineWidth must be equal StorePipelineWidth!") 461 require(LoadPipelineWidth == exuParameters.LduCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 462 require(StorePipelineWidth == exuParameters.StuCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 463 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 464 val asidLen = coreParams.MMUAsidLen 465 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 466 val refillBothTlb = coreParams.refillBothTlb 467 val iwpuParam = coreParams.iwpuParameters 468 val dwpuParam = coreParams.dwpuParameters 469 val itlbParams = coreParams.itlbParameters 470 val ldtlbParams = coreParams.ldtlbParameters 471 val sttlbParams = coreParams.sttlbParameters 472 val pftlbParams = coreParams.pftlbParameters 473 val btlbParams = coreParams.btlbParameters 474 val l2tlbParams = coreParams.l2tlbParameters 475 val NumPerfCounters = coreParams.NumPerfCounters 476 477 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 478 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 479 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 480 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 481 482 val instBytes = if (HasCExtension) 2 else 4 483 val instOffsetBits = log2Ceil(instBytes) 484 485 val icacheParameters = coreParams.icacheParameters 486 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 487 488 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 489 // for constrained LR/SC loop 490 val LRSCCycles = 64 491 // for lr storm 492 val LRSCBackOff = 8 493 494 // cache hierarchy configurations 495 val l1BusDataWidth = 256 496 497 // load violation predict 498 val ResetTimeMax2Pow = 20 //1078576 499 val ResetTimeMin2Pow = 10 //1024 500 // wait table parameters 501 val WaitTableSize = 1024 502 val MemPredPCWidth = log2Up(WaitTableSize) 503 val LWTUse2BitCounter = true 504 // store set parameters 505 val SSITSize = WaitTableSize 506 val LFSTSize = 32 507 val SSIDWidth = log2Up(LFSTSize) 508 val LFSTWidth = 4 509 val StoreSetEnable = true // LWT will be disabled if SS is enabled 510 val LFSTEnable = false 511 val loadExuConfigs = coreParams.loadExuConfigs 512 val storeExuConfigs = coreParams.storeExuConfigs 513 514 val intExuConfigs = coreParams.intExuConfigs 515 516 val fpExuConfigs = coreParams.fpExuConfigs 517 518 val exuConfigs = coreParams.exuConfigs 519 520 val PCntIncrStep: Int = 6 521 val numPCntHc: Int = 25 522 val numPCntPtw: Int = 19 523 524 val numCSRPCntFrontend = 8 525 val numCSRPCntCtrl = 8 526 val numCSRPCntLsu = 8 527 val numCSRPCntHc = 5 528 val printEventCoding = true 529} 530