1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 PathHistoryLength: Int = 16, 66 BtbSize: Int = 2048, 67 JbtacSize: Int = 1024, 68 JbtacBanks: Int = 8, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 UBtbWays: Int = 16, 72 BtbWays: Int = 2, 73 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 74 // Sets Hist Tag 75 Seq(( 128*8, 2, 7), 76 ( 128*8, 4, 7), 77 ( 256*8, 8, 8), 78 ( 256*8, 16, 8), 79 ( 128*8, 32, 9), 80 ( 128*8, 65, 9)), 81 TageBanks: Int = 2, 82 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 83 // Sets Hist Tag 84 Seq(( 512, 0, 0), 85 ( 256, 4, 8), 86 ( 256, 8, 8), 87 ( 512, 12, 8), 88 ( 512, 16, 8), 89 ( 512, 32, 8)), 90 SCNRows: Int = 1024, 91 SCNTables: Int = 6, 92 SCCtrBits: Int = 6, 93 numBr: Int = 2, 94 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 95 ((resp_in: BranchPredictionResp, p: Parameters) => { 96 // val loop = Module(new LoopPredictor) 97 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 98 // else Module(new Tage) } 99 // else { Module(new FakeTage) }) 100 val ftb = Module(new FTB()(p)) 101 val ubtb = Module(new MicroBTB()(p)) 102 val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 // val tage = Module(new Tage()(p)) 107 // val fake = Module(new FakePredictor()(p)) 108 109 // val preds = Seq(loop, tage, btb, ubtb, bim) 110 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 bim.io.in.bits.resp_in(0) := resp_in 119 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 120 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 121 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 122 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 123 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 124 125 (preds, ras.io.out.resp) 126 }), 127 IBufSize: Int = 48, 128 DecodeWidth: Int = 6, 129 RenameWidth: Int = 6, 130 CommitWidth: Int = 6, 131 FtqSize: Int = 64, 132 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 133 IssQueSize: Int = 16, 134 NRPhyRegs: Int = 192, 135 LoadQueueSize: Int = 80, 136 StoreQueueSize: Int = 64, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 LoadPipelineWidth: Int = 2, 158 StorePipelineWidth: Int = 2, 159 StoreBufferSize: Int = 16, 160 StoreBufferThreshold: Int = 7, 161 EnableLoadToLoadForward: Boolean = false, 162 EnableFastForward: Boolean = false, 163 EnableLdVioCheckAfterReset: Boolean = true, 164 EnableSoftPrefetchAfterReset: Boolean = true, 165 EnableCacheErrorAfterReset: Boolean = true, 166 RefillSize: Int = 512, 167 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 168 itlbParameters: TLBParameters = TLBParameters( 169 name = "itlb", 170 fetchi = true, 171 useDmode = false, 172 sameCycle = false, 173 missSameCycle = true, 174 normalNWays = 32, 175 normalReplacer = Some("plru"), 176 superNWays = 4, 177 superReplacer = Some("plru"), 178 shouldBlock = true 179 ), 180 ldtlbParameters: TLBParameters = TLBParameters( 181 name = "ldtlb", 182 normalNSets = 128, 183 normalNWays = 1, 184 normalAssociative = "sa", 185 normalReplacer = Some("setplru"), 186 superNWays = 8, 187 normalAsVictim = true, 188 outReplace = true, 189 partialStaticPMP = true, 190 saveLevel = true 191 ), 192 sttlbParameters: TLBParameters = TLBParameters( 193 name = "sttlb", 194 normalNSets = 128, 195 normalNWays = 1, 196 normalAssociative = "sa", 197 normalReplacer = Some("setplru"), 198 superNWays = 8, 199 normalAsVictim = true, 200 outReplace = true, 201 partialStaticPMP = true, 202 saveLevel = true 203 ), 204 refillBothTlb: Boolean = false, 205 btlbParameters: TLBParameters = TLBParameters( 206 name = "btlb", 207 normalNSets = 1, 208 normalNWays = 64, 209 superNWays = 4, 210 ), 211 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 212 NumPerfCounters: Int = 16, 213 icacheParameters: ICacheParameters = ICacheParameters( 214 tagECC = Some("parity"), 215 dataECC = Some("parity"), 216 replacer = Some("setplru"), 217 nMissEntries = 2, 218 nReleaseEntries = 2, 219 nProbeEntries = 2, 220 nPrefetchEntries = 4, 221 hasPrefetch = false, 222 ), 223 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 224 tagECC = Some("secded"), 225 dataECC = Some("secded"), 226 replacer = Some("setplru"), 227 nMissEntries = 16, 228 nProbeEntries = 8, 229 nReleaseEntries = 18 230 )), 231 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 232 name = "l2", 233 level = 2, 234 ways = 8, 235 sets = 1024, // default 512KB L2 236 prefetch = Some(huancun.prefetch.BOPParameters()) 237 )), 238 L2NBanks: Int = 1, 239 usePTWRepeater: Boolean = false, 240 softPTW: Boolean = false // dpi-c debug only 241){ 242 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 243 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 244 245 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 246 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 247 248 val fpExuConfigs = 249 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 250 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 251 252 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 253} 254 255case object DebugOptionsKey extends Field[DebugOptions] 256 257case class DebugOptions 258( 259 FPGAPlatform: Boolean = false, 260 EnableDifftest: Boolean = false, 261 AlwaysBasicDiff: Boolean = true, 262 EnableDebug: Boolean = false, 263 EnablePerfDebug: Boolean = true, 264 UseDRAMSim: Boolean = false 265) 266 267trait HasXSParameter { 268 269 implicit val p: Parameters 270 271 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 272 273 val coreParams = p(XSCoreParamsKey) 274 val env = p(DebugOptionsKey) 275 276 val XLEN = coreParams.XLEN 277 val minFLen = 32 278 val fLen = 64 279 def xLen = XLEN 280 281 val HasMExtension = coreParams.HasMExtension 282 val HasCExtension = coreParams.HasCExtension 283 val HasDiv = coreParams.HasDiv 284 val HasIcache = coreParams.HasICache 285 val HasDcache = coreParams.HasDCache 286 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 287 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 288 val AsidLength = coreParams.AsidLength 289 val AddrBytes = AddrBits / 8 // unused 290 val DataBits = XLEN 291 val DataBytes = DataBits / 8 292 val HasFPU = coreParams.HasFPU 293 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 294 val FetchWidth = coreParams.FetchWidth 295 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 296 val EnableBPU = coreParams.EnableBPU 297 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 298 val EnableRAS = coreParams.EnableRAS 299 val EnableLB = coreParams.EnableLB 300 val EnableLoop = coreParams.EnableLoop 301 val EnableSC = coreParams.EnableSC 302 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 303 val HistoryLength = coreParams.HistoryLength 304 val PathHistoryLength = coreParams.PathHistoryLength 305 val BtbSize = coreParams.BtbSize 306 // val BtbWays = 4 307 val BtbBanks = PredictWidth 308 // val BtbSets = BtbSize / BtbWays 309 val JbtacSize = coreParams.JbtacSize 310 val JbtacBanks = coreParams.JbtacBanks 311 val RasSize = coreParams.RasSize 312 313 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 314 coreParams.branchPredictor(resp_in, p) 315 } 316 val numBr = coreParams.numBr 317 val TageTableInfos = coreParams.TageTableInfos 318 319 320 val BankTageTableInfos = (0 until numBr).map(i => 321 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 322 ) 323 val TageBanks = coreParams.TageBanks 324 val SCNRows = coreParams.SCNRows 325 val SCCtrBits = coreParams.SCCtrBits 326 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 327 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 328 329 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 330 case (ntable, histlens) => 331 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 332 } 333 val ITTageTableInfos = coreParams.ITTageTableInfos 334 type FoldedHistoryInfo = Tuple2[Int, Int] 335 val foldedGHistInfos = 336 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 337 if (h > 0) 338 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 339 else 340 Set[FoldedHistoryInfo]() 341 }.reduce(_++_)).toSet ++ 342 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 343 if (h > 0) 344 Set((h, min(log2Ceil(nRows/TageBanks), h))) 345 else 346 Set[FoldedHistoryInfo]() 347 }.reduce(_++_)).toSet ++ 348 ITTageTableInfos.map{ case (nRows, h, t) => 349 if (h > 0) 350 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 351 else 352 Set[FoldedHistoryInfo]() 353 }.reduce(_++_)).toList 354 355 val CacheLineSize = coreParams.CacheLineSize 356 val CacheLineHalfWord = CacheLineSize / 16 357 val ExtHistoryLength = HistoryLength + 64 358 val UBtbWays = coreParams.UBtbWays 359 val BtbWays = coreParams.BtbWays 360 val IBufSize = coreParams.IBufSize 361 val DecodeWidth = coreParams.DecodeWidth 362 val RenameWidth = coreParams.RenameWidth 363 val CommitWidth = coreParams.CommitWidth 364 val FtqSize = coreParams.FtqSize 365 val IssQueSize = coreParams.IssQueSize 366 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 367 val NRPhyRegs = coreParams.NRPhyRegs 368 val PhyRegIdxWidth = log2Up(NRPhyRegs) 369 val RobSize = coreParams.RobSize 370 val IntRefCounterWidth = log2Ceil(RobSize) 371 val LoadQueueSize = coreParams.LoadQueueSize 372 val StoreQueueSize = coreParams.StoreQueueSize 373 val dpParams = coreParams.dpParams 374 val exuParameters = coreParams.exuParameters 375 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 376 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 377 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 378 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 379 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 380 val LoadPipelineWidth = coreParams.LoadPipelineWidth 381 val StorePipelineWidth = coreParams.StorePipelineWidth 382 val StoreBufferSize = coreParams.StoreBufferSize 383 val StoreBufferThreshold = coreParams.StoreBufferThreshold 384 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 385 val EnableFastForward = coreParams.EnableFastForward 386 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 387 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 388 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 389 val RefillSize = coreParams.RefillSize 390 val asidLen = coreParams.MMUAsidLen 391 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 392 val refillBothTlb = coreParams.refillBothTlb 393 val itlbParams = coreParams.itlbParameters 394 val ldtlbParams = coreParams.ldtlbParameters 395 val sttlbParams = coreParams.sttlbParameters 396 val btlbParams = coreParams.btlbParameters 397 val l2tlbParams = coreParams.l2tlbParameters 398 val NumPerfCounters = coreParams.NumPerfCounters 399 400 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 401 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 402 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 403 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 404 405 val instBytes = if (HasCExtension) 2 else 4 406 val instOffsetBits = log2Ceil(instBytes) 407 408 val icacheParameters = coreParams.icacheParameters 409 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 410 411 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 412 // for constrained LR/SC loop 413 val LRSCCycles = 64 414 // for lr storm 415 val LRSCBackOff = 8 416 417 // cache hierarchy configurations 418 val l1BusDataWidth = 256 419 420 // load violation predict 421 val ResetTimeMax2Pow = 20 //1078576 422 val ResetTimeMin2Pow = 10 //1024 423 // wait table parameters 424 val WaitTableSize = 1024 425 val MemPredPCWidth = log2Up(WaitTableSize) 426 val LWTUse2BitCounter = true 427 // store set parameters 428 val SSITSize = WaitTableSize 429 val LFSTSize = 32 430 val SSIDWidth = log2Up(LFSTSize) 431 val LFSTWidth = 4 432 val StoreSetEnable = true // LWT will be disabled if SS is enabled 433 434 val loadExuConfigs = coreParams.loadExuConfigs 435 val storeExuConfigs = coreParams.storeExuConfigs 436 437 val intExuConfigs = coreParams.intExuConfigs 438 439 val fpExuConfigs = coreParams.fpExuConfigs 440 441 val exuConfigs = coreParams.exuConfigs 442 443 val PCntIncrStep: Int = 6 444 val numPCntHc: Int = 25 445 val numPCntPtw: Int = 19 446 447 val numCSRPCntFrontend = 8 448 val numCSRPCntCtrl = 8 449 val numCSRPCntLsu = 8 450 val numCSRPCntHc = 5 451} 452