1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31 32case object XSTileKey extends Field[Seq[XSCoreParameters]] 33 34case object XSCoreParamsKey extends Field[XSCoreParameters] 35 36case class XSCoreParameters 37( 38 HasPrefetch: Boolean = false, 39 HartId: Int = 0, 40 XLEN: Int = 64, 41 HasMExtension: Boolean = true, 42 HasCExtension: Boolean = true, 43 HasDiv: Boolean = true, 44 HasICache: Boolean = true, 45 HasDCache: Boolean = true, 46 AddrBits: Int = 64, 47 VAddrBits: Int = 39, 48 PAddrBits: Int = 40, 49 HasFPU: Boolean = true, 50 HasCustomCSRCacheOp: Boolean = true, 51 FetchWidth: Int = 8, 52 AsidLength: Int = 16, 53 EnableBPU: Boolean = true, 54 EnableBPD: Boolean = true, 55 EnableRAS: Boolean = true, 56 EnableLB: Boolean = false, 57 EnableLoop: Boolean = true, 58 EnableSC: Boolean = true, 59 EnbaleTlbDebug: Boolean = false, 60 EnableJal: Boolean = false, 61 EnableUBTB: Boolean = true, 62 HistoryLength: Int = 64, 63 PathHistoryLength: Int = 16, 64 BtbSize: Int = 2048, 65 JbtacSize: Int = 1024, 66 JbtacBanks: Int = 8, 67 RasSize: Int = 32, 68 CacheLineSize: Int = 512, 69 UBtbWays: Int = 16, 70 BtbWays: Int = 2, 71 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 72 ((resp_in: BranchPredictionResp, p: Parameters) => { 73 // val loop = Module(new LoopPredictor) 74 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 75 // else Module(new Tage) } 76 // else { Module(new FakeTage) }) 77 val ftb = Module(new FTB()(p)) 78 val ubtb = Module(new MicroBTB()(p)) 79 val bim = Module(new BIM()(p)) 80 val tage = Module(new Tage_SC()(p)) 81 val ras = Module(new RAS()(p)) 82 val ittage = Module(new ITTage()(p)) 83 // val tage = Module(new Tage()(p)) 84 // val fake = Module(new FakePredictor()(p)) 85 86 // val preds = Seq(loop, tage, btb, ubtb, bim) 87 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 88 preds.map(_.io := DontCare) 89 90 // ubtb.io.resp_in(0) := resp_in 91 // bim.io.resp_in(0) := ubtb.io.resp 92 // btb.io.resp_in(0) := bim.io.resp 93 // tage.io.resp_in(0) := btb.io.resp 94 // loop.io.resp_in(0) := tage.io.resp 95 bim.io.in.bits.resp_in(0) := resp_in 96 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 97 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 98 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 99 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 100 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 101 102 (preds, ras.io.out.resp) 103 }), 104 IBufSize: Int = 48, 105 DecodeWidth: Int = 6, 106 RenameWidth: Int = 6, 107 CommitWidth: Int = 6, 108 FtqSize: Int = 64, 109 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 110 IssQueSize: Int = 16, 111 NRPhyRegs: Int = 192, 112 NRIntReadPorts: Int = 14, 113 NRIntWritePorts: Int = 8, 114 NRFpReadPorts: Int = 14, 115 NRFpWritePorts: Int = 8, 116 LoadQueueSize: Int = 80, 117 StoreQueueSize: Int = 64, 118 RobSize: Int = 256, 119 dpParams: DispatchParameters = DispatchParameters( 120 IntDqSize = 16, 121 FpDqSize = 16, 122 LsDqSize = 16, 123 IntDqDeqWidth = 4, 124 FpDqDeqWidth = 4, 125 LsDqDeqWidth = 4 126 ), 127 exuParameters: ExuParameters = ExuParameters( 128 JmpCnt = 1, 129 AluCnt = 4, 130 MulCnt = 0, 131 MduCnt = 2, 132 FmacCnt = 4, 133 FmiscCnt = 2, 134 FmiscDivSqrtCnt = 0, 135 LduCnt = 2, 136 StuCnt = 2 137 ), 138 LoadPipelineWidth: Int = 2, 139 StorePipelineWidth: Int = 2, 140 StoreBufferSize: Int = 16, 141 StoreBufferThreshold: Int = 7, 142 EnableFastForward: Boolean = true, 143 EnableLdVioCheckAfterReset: Boolean = true, 144 RefillSize: Int = 512, 145 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 146 itlbParameters: TLBParameters = TLBParameters( 147 name = "itlb", 148 fetchi = true, 149 useDmode = false, 150 sameCycle = true, 151 normalNWays = 32, 152 normalReplacer = Some("plru"), 153 superNWays = 4, 154 superReplacer = Some("plru"), 155 shouldBlock = true 156 ), 157 ldtlbParameters: TLBParameters = TLBParameters( 158 name = "ldtlb", 159 normalNSets = 128, 160 normalNWays = 1, 161 normalAssociative = "sa", 162 normalReplacer = Some("setplru"), 163 superNWays = 8, 164 normalAsVictim = true, 165 outReplace = true 166 ), 167 sttlbParameters: TLBParameters = TLBParameters( 168 name = "sttlb", 169 normalNSets = 128, 170 normalNWays = 1, 171 normalAssociative = "sa", 172 normalReplacer = Some("setplru"), 173 superNWays = 8, 174 normalAsVictim = true, 175 outReplace = true 176 ), 177 refillBothTlb: Boolean = false, 178 btlbParameters: TLBParameters = TLBParameters( 179 name = "btlb", 180 normalNSets = 1, 181 normalNWays = 64, 182 superNWays = 4, 183 ), 184 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 185 NumPMP: Int = 16, // 0 or 16 or 64 186 NumPMA: Int = 16, 187 NumPerfCounters: Int = 16, 188 icacheParameters: ICacheParameters = ICacheParameters( 189 tagECC = Some("parity"), 190 dataECC = Some("parity"), 191 replacer = Some("setplru"), 192 nMissEntries = 2 193 ), 194 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 195 tagECC = Some("secded"), 196 dataECC = Some("secded"), 197 replacer = Some("setplru"), 198 nMissEntries = 16, 199 nProbeEntries = 16, 200 nReleaseEntries = 32 201 )), 202 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 203 name = "l2", 204 level = 2, 205 ways = 8, 206 sets = 1024, // default 512KB L2 207 prefetch = Some(huancun.prefetch.BOPParameters()) 208 )), 209 L2NBanks: Int = 1, 210 usePTWRepeater: Boolean = false, 211 softPTW: Boolean = false // dpi-c debug only 212){ 213 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 214 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 215 216 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 217 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 218 219 val fpExuConfigs = 220 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 221 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 222 223 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 224} 225 226case object DebugOptionsKey extends Field[DebugOptions] 227 228case class DebugOptions 229( 230 FPGAPlatform: Boolean = true, 231 EnableDebug: Boolean = true, 232 EnablePerfDebug: Boolean = true, 233 UseDRAMSim: Boolean = false 234) 235 236trait HasXSParameter { 237 238 implicit val p: Parameters 239 240 val coreParams = p(XSCoreParamsKey) 241 val env = p(DebugOptionsKey) 242 243 val XLEN = coreParams.XLEN 244 val hardId = coreParams.HartId 245 val minFLen = 32 246 val fLen = 64 247 def xLen = XLEN 248 249 val HasMExtension = coreParams.HasMExtension 250 val HasCExtension = coreParams.HasCExtension 251 val HasDiv = coreParams.HasDiv 252 val HasIcache = coreParams.HasICache 253 val HasDcache = coreParams.HasDCache 254 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 255 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 256 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 257 val AsidLength = coreParams.AsidLength 258 val AddrBytes = AddrBits / 8 // unused 259 val DataBits = XLEN 260 val DataBytes = DataBits / 8 261 val HasFPU = coreParams.HasFPU 262 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 263 val FetchWidth = coreParams.FetchWidth 264 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 265 val EnableBPU = coreParams.EnableBPU 266 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 267 val EnableRAS = coreParams.EnableRAS 268 val EnableLB = coreParams.EnableLB 269 val EnableLoop = coreParams.EnableLoop 270 val EnableSC = coreParams.EnableSC 271 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 272 val HistoryLength = coreParams.HistoryLength 273 val PathHistoryLength = coreParams.PathHistoryLength 274 val BtbSize = coreParams.BtbSize 275 // val BtbWays = 4 276 val BtbBanks = PredictWidth 277 // val BtbSets = BtbSize / BtbWays 278 val JbtacSize = coreParams.JbtacSize 279 val JbtacBanks = coreParams.JbtacBanks 280 val RasSize = coreParams.RasSize 281 282 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 283 coreParams.branchPredictor(resp_in, p) 284 } 285 286 val CacheLineSize = coreParams.CacheLineSize 287 val CacheLineHalfWord = CacheLineSize / 16 288 val ExtHistoryLength = HistoryLength + 64 289 val UBtbWays = coreParams.UBtbWays 290 val BtbWays = coreParams.BtbWays 291 val IBufSize = coreParams.IBufSize 292 val DecodeWidth = coreParams.DecodeWidth 293 val RenameWidth = coreParams.RenameWidth 294 val CommitWidth = coreParams.CommitWidth 295 val FtqSize = coreParams.FtqSize 296 val IssQueSize = coreParams.IssQueSize 297 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 298 val NRPhyRegs = coreParams.NRPhyRegs 299 val PhyRegIdxWidth = log2Up(NRPhyRegs) 300 val RobSize = coreParams.RobSize 301 val IntRefCounterWidth = log2Ceil(RobSize) 302 val StdFreeListSize = NRPhyRegs - 32 303 val MEFreeListSize = NRPhyRegs 304 val LoadQueueSize = coreParams.LoadQueueSize 305 val StoreQueueSize = coreParams.StoreQueueSize 306 val dpParams = coreParams.dpParams 307 val exuParameters = coreParams.exuParameters 308 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 309 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 310 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 311 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 312 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 313 val LoadPipelineWidth = coreParams.LoadPipelineWidth 314 val StorePipelineWidth = coreParams.StorePipelineWidth 315 val StoreBufferSize = coreParams.StoreBufferSize 316 val StoreBufferThreshold = coreParams.StoreBufferThreshold 317 val EnableFastForward = coreParams.EnableFastForward 318 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 319 val RefillSize = coreParams.RefillSize 320 val asidLen = coreParams.MMUAsidLen 321 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 322 val refillBothTlb = coreParams.refillBothTlb 323 val itlbParams = coreParams.itlbParameters 324 val ldtlbParams = coreParams.ldtlbParameters 325 val sttlbParams = coreParams.sttlbParameters 326 val btlbParams = coreParams.btlbParameters 327 val l2tlbParams = coreParams.l2tlbParameters 328 val NumPMP = coreParams.NumPMP 329 val NumPMA = coreParams.NumPMA 330 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 331 val NumPerfCounters = coreParams.NumPerfCounters 332 333 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 334 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 335 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 336 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 337 338 val instBytes = if (HasCExtension) 2 else 4 339 val instOffsetBits = log2Ceil(instBytes) 340 341 val icacheParameters = coreParams.icacheParameters 342 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 343 344 val LRSCCycles = 100 345 346 // cache hierarchy configurations 347 val l1BusDataWidth = 256 348 349 // load violation predict 350 val ResetTimeMax2Pow = 20 //1078576 351 val ResetTimeMin2Pow = 10 //1024 352 // wait table parameters 353 val WaitTableSize = 1024 354 val MemPredPCWidth = log2Up(WaitTableSize) 355 val LWTUse2BitCounter = true 356 // store set parameters 357 val SSITSize = WaitTableSize 358 val LFSTSize = 32 359 val SSIDWidth = log2Up(LFSTSize) 360 val LFSTWidth = 4 361 val StoreSetEnable = true // LWT will be disabled if SS is enabled 362 363 val loadExuConfigs = coreParams.loadExuConfigs 364 val storeExuConfigs = coreParams.storeExuConfigs 365 366 val intExuConfigs = coreParams.intExuConfigs 367 368 val fpExuConfigs = coreParams.fpExuConfigs 369 370 val exuConfigs = coreParams.exuConfigs 371 372 val PCntIncrStep: Int = 6 373 val numPCntHc: Int = 25 374 val numPCntPtw: Int = 19 375 376 val numCSRPCntFrontend = 8 377 val numCSRPCntCtrl = 8 378 val numCSRPCntLsu = 8 379 val numCSRPCntHc = 5 380 val print_perfcounter = false 381} 382