1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 16, 90 RasSpecSize: Int = 32, 91 RasCtrSize: Int = 3, 92 CacheLineSize: Int = 512, 93 FtbWays: Int = 4, 94 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 95 // Sets Hist Tag 96 // Seq(( 2048, 2, 8), 97 // ( 2048, 9, 8), 98 // ( 2048, 13, 8), 99 // ( 2048, 20, 8), 100 // ( 2048, 26, 8), 101 // ( 2048, 44, 8), 102 // ( 2048, 73, 8), 103 // ( 2048, 256, 8)), 104 Seq(( 4096, 8, 8), 105 ( 4096, 13, 8), 106 ( 4096, 32, 8), 107 ( 4096, 119, 8)), 108 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 109 // Sets Hist Tag 110 Seq(( 256, 4, 9), 111 ( 256, 8, 9), 112 ( 512, 13, 9), 113 ( 512, 16, 9), 114 ( 512, 32, 9)), 115 SCNRows: Int = 512, 116 SCNTables: Int = 4, 117 SCCtrBits: Int = 6, 118 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 119 numBr: Int = 2, 120 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 121 ((resp_in: BranchPredictionResp, p: Parameters) => { 122 val ftb = Module(new FTB()(p)) 123 val ubtb =Module(new FauFTB()(p)) 124 // val bim = Module(new BIM()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(ubtb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 // ubtb.io.resp_in(0) := resp_in 132 // bim.io.resp_in(0) := ubtb.io.resp 133 // btb.io.resp_in(0) := bim.io.resp 134 // tage.io.resp_in(0) := btb.io.resp 135 // loop.io.resp_in(0) := tage.io.resp 136 ubtb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := ubtb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }), 144 ICacheECCForceError: Boolean = false, 145 IBufSize: Int = 48, 146 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 147 DecodeWidth: Int = 6, 148 RenameWidth: Int = 6, 149 CommitWidth: Int = 6, 150 MaxUopSize: Int = 65, 151 EnableRenameSnapshot: Boolean = true, 152 RenameSnapshotNum: Int = 4, 153 FtqSize: Int = 64, 154 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 155 IntLogicRegs: Int = 32, 156 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 157 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 158 VCONFIG_IDX: Int = 32, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 256, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 32, 175 dpParams: DispatchParameters = DispatchParameters( 176 IntDqSize = 16, 177 FpDqSize = 16, 178 LsDqSize = 18, 179 IntDqDeqWidth = 6, 180 FpDqDeqWidth = 6, 181 LsDqDeqWidth = 6, 182 ), 183 intPreg: PregParams = IntPregParams( 184 numEntries = 224, 185 numRead = None, 186 numWrite = None, 187 ), 188 vfPreg: VfPregParams = VfPregParams( 189 numEntries = 192, 190 numRead = Some(14), 191 numWrite = None, 192 ), 193 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 194 LoadPipelineWidth: Int = 3, 195 StorePipelineWidth: Int = 2, 196 VecLoadPipelineWidth: Int = 2, 197 VecStorePipelineWidth: Int = 2, 198 VecMemSrcInWidth: Int = 2, 199 VecMemInstWbWidth: Int = 1, 200 VecMemDispatchWidth: Int = 1, 201 StoreBufferSize: Int = 16, 202 StoreBufferThreshold: Int = 7, 203 EnsbufferWidth: Int = 2, 204 // ============ VLSU ============ 205 UsQueueSize: Int = 8, 206 VlFlowSize: Int = 32, 207 VlUopSize: Int = 32, 208 VsFlowL1Size: Int = 128, 209 VsFlowL2Size: Int = 32, 210 VsUopSize: Int = 32, 211 // ============================== 212 UncacheBufferSize: Int = 4, 213 EnableLoadToLoadForward: Boolean = false, 214 EnableFastForward: Boolean = true, 215 EnableLdVioCheckAfterReset: Boolean = true, 216 EnableSoftPrefetchAfterReset: Boolean = true, 217 EnableCacheErrorAfterReset: Boolean = true, 218 EnableAccurateLoadError: Boolean = true, 219 EnableUncacheWriteOutstanding: Boolean = false, 220 EnableStorePrefetchAtIssue: Boolean = false, 221 EnableStorePrefetchAtCommit: Boolean = false, 222 EnableAtCommitMissTrigger: Boolean = true, 223 EnableStorePrefetchSMS: Boolean = false, 224 EnableStorePrefetchSPB: Boolean = false, 225 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 226 ReSelectLen: Int = 7, // load replay queue replay select counter len 227 iwpuParameters: WPUParameters = WPUParameters( 228 enWPU = false, 229 algoName = "mmru", 230 isICache = true, 231 ), 232 dwpuParameters: WPUParameters = WPUParameters( 233 enWPU = false, 234 algoName = "mmru", 235 enCfPred = false, 236 isICache = false, 237 ), 238 itlbParameters: TLBParameters = TLBParameters( 239 name = "itlb", 240 fetchi = true, 241 useDmode = false, 242 NWays = 48, 243 ), 244 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 245 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 246 ldtlbParameters: TLBParameters = TLBParameters( 247 name = "ldtlb", 248 NWays = 48, 249 outReplace = false, 250 partialStaticPMP = true, 251 outsideRecvFlush = true, 252 saveLevel = true 253 ), 254 sttlbParameters: TLBParameters = TLBParameters( 255 name = "sttlb", 256 NWays = 48, 257 outReplace = false, 258 partialStaticPMP = true, 259 outsideRecvFlush = true, 260 saveLevel = true 261 ), 262 hytlbParameters: TLBParameters = TLBParameters( 263 name = "hytlb", 264 NWays = 48, 265 outReplace = false, 266 partialStaticPMP = true, 267 outsideRecvFlush = true, 268 saveLevel = true 269 ), 270 pftlbParameters: TLBParameters = TLBParameters( 271 name = "pftlb", 272 NWays = 48, 273 outReplace = false, 274 partialStaticPMP = true, 275 outsideRecvFlush = true, 276 saveLevel = true 277 ), 278 refillBothTlb: Boolean = false, 279 btlbParameters: TLBParameters = TLBParameters( 280 name = "btlb", 281 NWays = 48, 282 ), 283 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 284 NumPerfCounters: Int = 16, 285 icacheParameters: ICacheParameters = ICacheParameters( 286 tagECC = Some("parity"), 287 dataECC = Some("parity"), 288 replacer = Some("setplru"), 289 nMissEntries = 2, 290 nProbeEntries = 2, 291 nPrefetchEntries = 12, 292 nPrefBufferEntries = 32, 293 ), 294 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 295 tagECC = Some("secded"), 296 dataECC = Some("secded"), 297 replacer = Some("setplru"), 298 nMissEntries = 16, 299 nProbeEntries = 8, 300 nReleaseEntries = 18, 301 nMaxPrefetchEntry = 6, 302 )), 303 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 304 name = "l2", 305 ways = 8, 306 sets = 1024, // default 512KB L2 307 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 308 )), 309 L2NBanks: Int = 1, 310 usePTWRepeater: Boolean = false, 311 softTLB: Boolean = false, // dpi-c l1tlb debug only 312 softPTW: Boolean = false, // dpi-c l2tlb debug only 313 softPTWDelay: Int = 1 314){ 315 def vlWidth = log2Up(VLEN) + 1 316 317 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 318 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 319 320 val intSchdParams = { 321 implicit val schdType: SchedulerType = IntScheduler() 322 SchdBlockParams(Seq( 323 IssueBlockParams(Seq( 324 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 325 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 326 ), numEntries = IssueQueueSize, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 329 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 330 ), numEntries = IssueQueueSize, numEnq = 2), 331 IssueBlockParams(Seq( 332 ExeUnitParams("BJU0", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 333 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(10, 0)), Seq(IntRD(12, 1)))), 334 ), numEntries = IssueQueueSize, numEnq = 2), 335 IssueBlockParams(Seq( 336 ExeUnitParams("BJU2", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 337 ), numEntries = IssueQueueSize / 2, numEnq = 1), 338 IssueBlockParams(Seq( 339 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, I2vCfg, VSetRiWvfCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 1), VfWB(2, 0)), Seq(Seq(IntRD(5, 1)), Seq(IntRD(3, 1)))), 340 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 7, 1)), Seq(Seq(IntRD(1, Int.MaxValue)), Seq(IntRD(9, Int.MaxValue)))), 341 ), numEntries = IssueQueueSize, numEnq = 2), 342 ), 343 numPregs = intPreg.numEntries, 344 numDeqOutside = 0, 345 schdType = schdType, 346 rfDataWidth = intPreg.dataCfg.dataWidth, 347 numUopIn = dpParams.IntDqDeqWidth, 348 ) 349 } 350 val vfSchdParams = { 351 implicit val schdType: SchedulerType = VfScheduler() 352 SchdBlockParams(Seq( 353 IssueBlockParams(Seq( 354 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VppuCfg, F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 355 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfmaCfg, VimacCfg, VipuCfg, VfcvtCfg), Seq(VfWB(port = 1, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 356 ), numEntries = IssueQueueSize, numEnq = 2), 357 IssueBlockParams(Seq( 358 ExeUnitParams("VFEX2", Seq(VfdivCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 359 ), numEntries = IssueQueueSize, numEnq = 2), 360 ), 361 numPregs = vfPreg.numEntries, 362 numDeqOutside = 0, 363 schdType = schdType, 364 rfDataWidth = vfPreg.dataCfg.dataWidth, 365 numUopIn = dpParams.FpDqDeqWidth, 366 ) 367 } 368 369 val memSchdParams = { 370 implicit val schdType: SchedulerType = MemScheduler() 371 val rfDataWidth = 64 372 373 SchdBlockParams(Seq( 374 IssueBlockParams(Seq( 375 ExeUnitParams("STA0", Seq(StaCfg), Seq(), Seq(Seq(IntRD(3, 1)))), 376 ), numEntries = IssueQueueSize, numEnq = 2), 377 IssueBlockParams(Seq( 378 ExeUnitParams("HYU0", Seq(HyldaCfg, HystaCfg, MouCfg), Seq(IntWB(5, 0), VfWB(5, 0)), Seq(Seq(IntRD(6, 0)))), 379 ExeUnitParams("HYU1", Seq(FakeHystaCfg), Seq(), Seq()), // fake unit, used to create a new writeback port 380 ), numEntries = IssueQueueSize, numEnq = 2), 381 IssueBlockParams(Seq( 382 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(12, 0)))), 383 ), numEntries = IssueQueueSize, numEnq = 2), 384 IssueBlockParams(Seq( 385 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(13, 0)))), 386 ), numEntries = IssueQueueSize, numEnq = 2), 387 IssueBlockParams(Seq( 388 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 389 ), numEntries = IssueQueueSize, numEnq = 2), 390 IssueBlockParams(Seq( 391 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 1), VfRD(6, 0)))), 392 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 1), VfRD(10, Int.MaxValue)))), 393 ), numEntries = IssueQueueSize, numEnq = 4), 394 ), 395 numPregs = intPreg.numEntries max vfPreg.numEntries, 396 numDeqOutside = 0, 397 schdType = schdType, 398 rfDataWidth = rfDataWidth, 399 numUopIn = dpParams.LsDqDeqWidth, 400 ) 401 } 402 403 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 404 405 def iqWakeUpParams = { 406 Seq( 407 WakeUpConfig( 408 Seq("ALU0", "ALU1", "MUL0", "MUL1", "LDU0", "LDU1", "HYU0") -> 409 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "BJU2", "LDU0", "LDU1", "STA0", "STD0", "STD1", "HYU0") 410 ), 411 WakeUpConfig(Seq("IMISC0") -> Seq("VFEX0")), 412 ).flatten 413 } 414 415 def backendParams: BackendParams = backend.BackendParams( 416 Map( 417 IntScheduler() -> intSchdParams, 418 VfScheduler() -> vfSchdParams, 419 MemScheduler() -> memSchdParams, 420 ), 421 Seq( 422 intPreg, 423 vfPreg, 424 ), 425 iqWakeUpParams, 426 ) 427} 428 429case object DebugOptionsKey extends Field[DebugOptions] 430 431case class DebugOptions 432( 433 FPGAPlatform: Boolean = false, 434 EnableDifftest: Boolean = false, 435 AlwaysBasicDiff: Boolean = true, 436 EnableDebug: Boolean = false, 437 EnablePerfDebug: Boolean = true, 438 UseDRAMSim: Boolean = false, 439 EnableConstantin: Boolean = false, 440 EnableChiselDB: Boolean = false, 441 AlwaysBasicDB: Boolean = true, 442 EnableTopDown: Boolean = false, 443 EnableRollingDB: Boolean = false 444) 445 446trait HasXSParameter { 447 448 implicit val p: Parameters 449 450 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 451 452 val coreParams = p(XSCoreParamsKey) 453 val env = p(DebugOptionsKey) 454 455 val XLEN = coreParams.XLEN 456 val VLEN = coreParams.VLEN 457 val ELEN = coreParams.ELEN 458 val minFLen = 32 459 val fLen = 64 460 def xLen = XLEN 461 462 val HasMExtension = coreParams.HasMExtension 463 val HasCExtension = coreParams.HasCExtension 464 val HasDiv = coreParams.HasDiv 465 val HasIcache = coreParams.HasICache 466 val HasDcache = coreParams.HasDCache 467 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 468 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 469 val AsidLength = coreParams.AsidLength 470 val ReSelectLen = coreParams.ReSelectLen 471 val AddrBytes = AddrBits / 8 // unused 472 val DataBits = XLEN 473 val DataBytes = DataBits / 8 474 val VDataBytes = VLEN / 8 475 val HasFPU = coreParams.HasFPU 476 val HasVPU = coreParams.HasVPU 477 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 478 val FetchWidth = coreParams.FetchWidth 479 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 480 val EnableBPU = coreParams.EnableBPU 481 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 482 val EnableRAS = coreParams.EnableRAS 483 val EnableLB = coreParams.EnableLB 484 val EnableLoop = coreParams.EnableLoop 485 val EnableSC = coreParams.EnableSC 486 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 487 val HistoryLength = coreParams.HistoryLength 488 val EnableGHistDiff = coreParams.EnableGHistDiff 489 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 490 val UbtbGHRLength = coreParams.UbtbGHRLength 491 val UbtbSize = coreParams.UbtbSize 492 val EnableFauFTB = coreParams.EnableFauFTB 493 val FtbSize = coreParams.FtbSize 494 val FtbWays = coreParams.FtbWays 495 val RasSize = coreParams.RasSize 496 val RasSpecSize = coreParams.RasSpecSize 497 val RasCtrSize = coreParams.RasCtrSize 498 499 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 500 coreParams.branchPredictor(resp_in, p) 501 } 502 val numBr = coreParams.numBr 503 val TageTableInfos = coreParams.TageTableInfos 504 val TageBanks = coreParams.numBr 505 val SCNRows = coreParams.SCNRows 506 val SCCtrBits = coreParams.SCCtrBits 507 val SCHistLens = coreParams.SCHistLens 508 val SCNTables = coreParams.SCNTables 509 510 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 511 case ((n, cb), h) => (n, cb, h) 512 } 513 val ITTageTableInfos = coreParams.ITTageTableInfos 514 type FoldedHistoryInfo = Tuple2[Int, Int] 515 val foldedGHistInfos = 516 (TageTableInfos.map{ case (nRows, h, t) => 517 if (h > 0) 518 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 519 else 520 Set[FoldedHistoryInfo]() 521 }.reduce(_++_).toSet ++ 522 SCTableInfos.map{ case (nRows, _, h) => 523 if (h > 0) 524 Set((h, min(log2Ceil(nRows/TageBanks), h))) 525 else 526 Set[FoldedHistoryInfo]() 527 }.reduce(_++_).toSet ++ 528 ITTageTableInfos.map{ case (nRows, h, t) => 529 if (h > 0) 530 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 531 else 532 Set[FoldedHistoryInfo]() 533 }.reduce(_++_) ++ 534 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 535 ).toList 536 537 538 539 val CacheLineSize = coreParams.CacheLineSize 540 val CacheLineHalfWord = CacheLineSize / 16 541 val ExtHistoryLength = HistoryLength + 64 542 val ICacheECCForceError = coreParams.ICacheECCForceError 543 val IBufSize = coreParams.IBufSize 544 val IBufNBank = coreParams.IBufNBank 545 val DecodeWidth = coreParams.DecodeWidth 546 val RenameWidth = coreParams.RenameWidth 547 val CommitWidth = coreParams.CommitWidth 548 val MaxUopSize = coreParams.MaxUopSize 549 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 550 val RenameSnapshotNum = coreParams.RenameSnapshotNum 551 val FtqSize = coreParams.FtqSize 552 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 553 val IntLogicRegs = coreParams.IntLogicRegs 554 val FpLogicRegs = coreParams.FpLogicRegs 555 val VecLogicRegs = coreParams.VecLogicRegs 556 val VCONFIG_IDX = coreParams.VCONFIG_IDX 557 val IntPhyRegs = coreParams.intPreg.numEntries 558 val VfPhyRegs = coreParams.vfPreg.numEntries 559 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 560 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 561 val RobSize = coreParams.RobSize 562 val RabSize = coreParams.RabSize 563 val VTypeBufferSize = coreParams.VTypeBufferSize 564 val IntRefCounterWidth = log2Ceil(RobSize) 565 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 566 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 567 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 568 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 569 val LoadQueueRARSize = coreParams.LoadQueueRARSize 570 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 571 val RollbackGroupSize = coreParams.RollbackGroupSize 572 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 573 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 574 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 575 val StoreQueueSize = coreParams.StoreQueueSize 576 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 577 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 578 val VlsQueueSize = coreParams.VlsQueueSize 579 val dpParams = coreParams.dpParams 580 581 def backendParams: BackendParams = coreParams.backendParams 582 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 583 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 584 585 val NumRedirect = backendParams.numRedirect 586 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 587 val FtqRedirectAheadNum = NumRedirect 588 val LoadPipelineWidth = coreParams.LoadPipelineWidth 589 val StorePipelineWidth = coreParams.StorePipelineWidth 590 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 591 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 592 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 593 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 594 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 595 val StoreBufferSize = coreParams.StoreBufferSize 596 val StoreBufferThreshold = coreParams.StoreBufferThreshold 597 val EnsbufferWidth = coreParams.EnsbufferWidth 598 val UsQueueSize = coreParams.UsQueueSize 599 val VlFlowSize = coreParams.VlFlowSize 600 val VlUopSize = coreParams.VlUopSize 601 val VsFlowL1Size = coreParams.VsFlowL1Size 602 val VsFlowL2Size = coreParams.VsFlowL2Size 603 val VsUopSize = coreParams.VsUopSize 604 val UncacheBufferSize = coreParams.UncacheBufferSize 605 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 606 val EnableFastForward = coreParams.EnableFastForward 607 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 608 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 609 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 610 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 611 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 612 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 613 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 614 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 615 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 616 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 617 val asidLen = coreParams.MMUAsidLen 618 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 619 val refillBothTlb = coreParams.refillBothTlb 620 val iwpuParam = coreParams.iwpuParameters 621 val dwpuParam = coreParams.dwpuParameters 622 val itlbParams = coreParams.itlbParameters 623 val ldtlbParams = coreParams.ldtlbParameters 624 val sttlbParams = coreParams.sttlbParameters 625 val hytlbParams = coreParams.hytlbParameters 626 val pftlbParams = coreParams.pftlbParameters 627 val btlbParams = coreParams.btlbParameters 628 val l2tlbParams = coreParams.l2tlbParameters 629 val NumPerfCounters = coreParams.NumPerfCounters 630 631 val instBytes = if (HasCExtension) 2 else 4 632 val instOffsetBits = log2Ceil(instBytes) 633 634 val icacheParameters = coreParams.icacheParameters 635 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 636 637 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 638 // for constrained LR/SC loop 639 val LRSCCycles = 64 640 // for lr storm 641 val LRSCBackOff = 8 642 643 // cache hierarchy configurations 644 val l1BusDataWidth = 256 645 646 // load violation predict 647 val ResetTimeMax2Pow = 20 //1078576 648 val ResetTimeMin2Pow = 10 //1024 649 // wait table parameters 650 val WaitTableSize = 1024 651 val MemPredPCWidth = log2Up(WaitTableSize) 652 val LWTUse2BitCounter = true 653 // store set parameters 654 val SSITSize = WaitTableSize 655 val LFSTSize = 32 656 val SSIDWidth = log2Up(LFSTSize) 657 val LFSTWidth = 4 658 val StoreSetEnable = true // LWT will be disabled if SS is enabled 659 val LFSTEnable = true 660 661 val PCntIncrStep: Int = 6 662 val numPCntHc: Int = 25 663 val numPCntPtw: Int = 19 664 665 val numCSRPCntFrontend = 8 666 val numCSRPCntCtrl = 8 667 val numCSRPCntLsu = 8 668 val numCSRPCntHc = 5 669 val printEventCoding = true 670 671 // Parameters for Sdtrig extension 672 protected val TriggerNum = 4 673 protected val TriggerChainMaxLength = 2 674} 675