1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 29import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 30import freechips.rocketchip.diplomacy.AddressSet 31 32case object XSCoreParamsKey extends Field[XSCoreParameters] 33 34case class XSCoreParameters 35( 36 HasPrefetch: Boolean = false, 37 HartId: Int = 0, 38 XLEN: Int = 64, 39 HasMExtension: Boolean = true, 40 HasCExtension: Boolean = true, 41 HasDiv: Boolean = true, 42 HasICache: Boolean = true, 43 HasDCache: Boolean = true, 44 AddrBits: Int = 64, 45 VAddrBits: Int = 39, 46 PAddrBits: Int = 40, 47 HasFPU: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 32, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 val ittage = Module(new ITTage()(p)) 79 // val tage = Module(new Tage()(p)) 80 // val fake = Module(new FakePredictor()(p)) 81 82 // val preds = Seq(loop, tage, btb, ubtb, bim) 83 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 84 preds.map(_.io := DontCare) 85 86 // ubtb.io.resp_in(0) := resp_in 87 // bim.io.resp_in(0) := ubtb.io.resp 88 // btb.io.resp_in(0) := bim.io.resp 89 // tage.io.resp_in(0) := btb.io.resp 90 // loop.io.resp_in(0) := tage.io.resp 91 bim.io.in.bits.resp_in(0) := resp_in 92 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 93 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 94 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 95 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 96 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 97 98 (preds, ras.io.out.resp) 99 }), 100 101 102 EnableL1plusPrefetcher: Boolean = true, 103 IBufSize: Int = 48, 104 DecodeWidth: Int = 6, 105 RenameWidth: Int = 6, 106 CommitWidth: Int = 6, 107 BrqSize: Int = 32, 108 FtqSize: Int = 64, 109 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 110 IssQueSize: Int = 16, 111 NRPhyRegs: Int = 160, 112 NRIntReadPorts: Int = 14, 113 NRIntWritePorts: Int = 8, 114 NRFpReadPorts: Int = 14, 115 NRFpWritePorts: Int = 8, 116 LoadQueueSize: Int = 64, 117 StoreQueueSize: Int = 48, 118 RoqSize: Int = 192, 119 EnableIntMoveElim: Boolean = true, 120 IntRefCounterWidth: Int = 2, 121 dpParams: DispatchParameters = DispatchParameters( 122 IntDqSize = 16, 123 FpDqSize = 16, 124 LsDqSize = 16, 125 IntDqDeqWidth = 4, 126 FpDqDeqWidth = 4, 127 LsDqDeqWidth = 4 128 ), 129 exuParameters: ExuParameters = ExuParameters( 130 JmpCnt = 1, 131 AluCnt = 4, 132 MulCnt = 0, 133 MduCnt = 2, 134 FmacCnt = 4, 135 FmiscCnt = 2, 136 FmiscDivSqrtCnt = 0, 137 LduCnt = 2, 138 StuCnt = 2 139 ), 140 LoadPipelineWidth: Int = 2, 141 StorePipelineWidth: Int = 2, 142 StoreBufferSize: Int = 16, 143 StoreBufferThreshold: Int = 7, 144 EnableFastForward: Boolean = true, 145 RefillSize: Int = 512, 146 itlbParameters: TLBParameters = TLBParameters( 147 name = "itlb", 148 fetchi = true, 149 useDmode = false, 150 sameCycle = true, 151 normalReplacer = Some("plru"), 152 superReplacer = Some("plru"), 153 shouldBlock = true 154 ), 155 ldtlbParameters: TLBParameters = TLBParameters( 156 name = "ldtlb", 157 normalNSets = 128, 158 normalNWays = 1, 159 normalAssociative = "sa", 160 normalReplacer = Some("setplru"), 161 superNWays = 8, 162 normalAsVictim = true, 163 outReplace = true 164 ), 165 sttlbParameters: TLBParameters = TLBParameters( 166 name = "sttlb", 167 normalNSets = 128, 168 normalNWays = 1, 169 normalAssociative = "sa", 170 normalReplacer = Some("setplru"), 171 superNWays = 8, 172 normalAsVictim = true, 173 outReplace = true 174 ), 175 btlbParameters: TLBParameters = TLBParameters( 176 name = "btlb", 177 normalNSets = 1, 178 normalNWays = 64, 179 superNWays = 4, 180 ), 181 useBTlb: Boolean = false, 182 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 183 NumPerfCounters: Int = 16, 184 icacheParameters: ICacheParameters = ICacheParameters( 185 tagECC = Some("parity"), 186 dataECC = Some("parity"), 187 replacer = Some("setplru"), 188 nMissEntries = 2 189 ), 190 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 191 tagECC = Some("secded"), 192 dataECC = Some("secded"), 193 replacer = Some("setplru"), 194 nMissEntries = 8 195 ), 196 dcacheParameters: DCacheParameters = DCacheParameters( 197 tagECC = Some("secded"), 198 dataECC = Some("secded"), 199 replacer = Some("setplru"), 200 nMissEntries = 16, 201 nProbeEntries = 16, 202 nReleaseEntries = 16, 203 nStoreReplayEntries = 16 204 ), 205 L2Size: Int = 512 * 1024, // 512KB 206 L2NWays: Int = 8, 207 useFakePTW: Boolean = false, 208 useFakeDCache: Boolean = false, 209 useFakeL1plusCache: Boolean = false, 210 useFakeL2Cache: Boolean = false 211){ 212 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 213 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 214 215 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 216 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 217 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 218 219 val fpExuConfigs = 220 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 221 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 222 223 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 224} 225 226case object DebugOptionsKey extends Field[DebugOptions] 227 228case class DebugOptions 229( 230 FPGAPlatform: Boolean = true, 231 EnableDebug: Boolean = true, 232 EnablePerfDebug: Boolean = true, 233 UseDRAMSim: Boolean = false 234) 235 236trait HasXSParameter { 237 238 implicit val p: Parameters 239 240 val coreParams = p(XSCoreParamsKey) 241 val env = p(DebugOptionsKey) 242 243 val XLEN = coreParams.XLEN 244 val hardId = coreParams.HartId 245 val minFLen = 32 246 val fLen = 64 247 def xLen = XLEN 248 249 val HasMExtension = coreParams.HasMExtension 250 val HasCExtension = coreParams.HasCExtension 251 val HasDiv = coreParams.HasDiv 252 val HasIcache = coreParams.HasICache 253 val HasDcache = coreParams.HasDCache 254 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 255 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 256 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 257 val AddrBytes = AddrBits / 8 // unused 258 val DataBits = XLEN 259 val DataBytes = DataBits / 8 260 val HasFPU = coreParams.HasFPU 261 val FetchWidth = coreParams.FetchWidth 262 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 263 val EnableBPU = coreParams.EnableBPU 264 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 265 val EnableRAS = coreParams.EnableRAS 266 val EnableLB = coreParams.EnableLB 267 val EnableLoop = coreParams.EnableLoop 268 val EnableSC = coreParams.EnableSC 269 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 270 val HistoryLength = coreParams.HistoryLength 271 val PathHistoryLength = coreParams.PathHistoryLength 272 val BtbSize = coreParams.BtbSize 273 // val BtbWays = 4 274 val BtbBanks = PredictWidth 275 // val BtbSets = BtbSize / BtbWays 276 val JbtacSize = coreParams.JbtacSize 277 val JbtacBanks = coreParams.JbtacBanks 278 val RasSize = coreParams.RasSize 279 280 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 281 coreParams.branchPredictor(resp_in, p, enableSC) 282 } 283 284 val CacheLineSize = coreParams.CacheLineSize 285 val CacheLineHalfWord = CacheLineSize / 16 286 val ExtHistoryLength = HistoryLength + 64 287 val UBtbWays = coreParams.UBtbWays 288 val BtbWays = coreParams.BtbWays 289 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 290 val IBufSize = coreParams.IBufSize 291 val DecodeWidth = coreParams.DecodeWidth 292 val RenameWidth = coreParams.RenameWidth 293 val CommitWidth = coreParams.CommitWidth 294 val BrqSize = coreParams.BrqSize 295 val FtqSize = coreParams.FtqSize 296 val IssQueSize = coreParams.IssQueSize 297 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 298 val BrTagWidth = log2Up(BrqSize) 299 val NRPhyRegs = coreParams.NRPhyRegs 300 val PhyRegIdxWidth = log2Up(NRPhyRegs) 301 val RoqSize = coreParams.RoqSize 302 val EnableIntMoveElim = coreParams.EnableIntMoveElim 303 val IntRefCounterWidth = coreParams.IntRefCounterWidth 304 val StdFreeListSize = NRPhyRegs - 32 305 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 306 val MEFreeListSize = NRPhyRegs 307 val LoadQueueSize = coreParams.LoadQueueSize 308 val StoreQueueSize = coreParams.StoreQueueSize 309 val dpParams = coreParams.dpParams 310 val exuParameters = coreParams.exuParameters 311 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 312 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 313 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 314 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 315 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 316 val LoadPipelineWidth = coreParams.LoadPipelineWidth 317 val StorePipelineWidth = coreParams.StorePipelineWidth 318 val StoreBufferSize = coreParams.StoreBufferSize 319 val StoreBufferThreshold = coreParams.StoreBufferThreshold 320 val EnableFastForward = coreParams.EnableFastForward 321 val RefillSize = coreParams.RefillSize 322 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 323 val useBTlb = coreParams.useBTlb 324 val itlbParams = coreParams.itlbParameters 325 val ldtlbParams = coreParams.ldtlbParameters 326 val sttlbParams = coreParams.sttlbParameters 327 val btlbParams = coreParams.btlbParameters 328 val l2tlbParams = coreParams.l2tlbParameters 329 val NumPerfCounters = coreParams.NumPerfCounters 330 331 val instBytes = if (HasCExtension) 2 else 4 332 val instOffsetBits = log2Ceil(instBytes) 333 334 val icacheParameters = coreParams.icacheParameters 335 val l1plusCacheParameters = coreParams.l1plusCacheParameters 336 val dcacheParameters = coreParams.dcacheParameters 337 338 val LRSCCycles = 100 339 340 341 // cache hierarchy configurations 342 val l1BusDataWidth = 256 343 344 val useFakeDCache = coreParams.useFakeDCache 345 val useFakePTW = coreParams.useFakePTW 346 val useFakeL1plusCache = coreParams.useFakeL1plusCache 347 // L2 configurations 348 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 349 val L1BusWidth = 256 350 val L2Size = coreParams.L2Size 351 val L2BlockSize = 64 352 val L2NWays = coreParams.L2NWays 353 val L2NSets = L2Size / L2BlockSize / L2NWays 354 355 // L3 configurations 356 val L2BusWidth = 256 357 358 // icache prefetcher 359 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 360 enable = true, 361 _type = "stream", 362 streamParams = StreamPrefetchParameters( 363 streamCnt = 2, 364 streamSize = 4, 365 ageWidth = 4, 366 blockBytes = l1plusCacheParameters.blockBytes, 367 reallocStreamOnMissInstantly = true, 368 cacheName = "icache" 369 ) 370 ) 371 372 // dcache prefetcher 373 val l2PrefetcherParameters = L2PrefetcherParameters( 374 enable = true, 375 _type = "bop", // "stream" or "bop" 376 streamParams = StreamPrefetchParameters( 377 streamCnt = 4, 378 streamSize = 4, 379 ageWidth = 4, 380 blockBytes = L2BlockSize, 381 reallocStreamOnMissInstantly = true, 382 cacheName = "dcache" 383 ), 384 bopParams = BOPParameters( 385 rrTableEntries = 256, 386 rrTagBits = 12, 387 scoreBits = 5, 388 roundMax = 50, 389 badScore = 1, 390 blockBytes = L2BlockSize, 391 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 392 ), 393 ) 394 395 // load violation predict 396 val ResetTimeMax2Pow = 20 //1078576 397 val ResetTimeMin2Pow = 10 //1024 398 // wait table parameters 399 val WaitTableSize = 1024 400 val MemPredPCWidth = log2Up(WaitTableSize) 401 val LWTUse2BitCounter = true 402 // store set parameters 403 val SSITSize = WaitTableSize 404 val LFSTSize = 32 405 val SSIDWidth = log2Up(LFSTSize) 406 val LFSTWidth = 4 407 val StoreSetEnable = true // LWT will be disabled if SS is enabled 408 409 val loadExuConfigs = coreParams.loadExuConfigs 410 val storeExuConfigs = coreParams.storeExuConfigs 411 412 val intExuConfigs = coreParams.intExuConfigs 413 414 val fpExuConfigs = coreParams.fpExuConfigs 415 416 val exuConfigs = coreParams.exuConfigs 417 418} 419