1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import system.CVMParamskey 25import xiangshan.backend.datapath.RdConfig._ 26import xiangshan.backend.datapath.WbConfig._ 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasBitmapCheck: Boolean = false, 65 HasBitmapCheckDefault: Boolean = false, 66 HasMExtension: Boolean = true, 67 HasCExtension: Boolean = true, 68 HasHExtension: Boolean = true, 69 HasDiv: Boolean = true, 70 HasICache: Boolean = true, 71 HasDCache: Boolean = true, 72 AddrBits: Int = 64, 73 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 74 VAddrBitsSv39: Int = 39, 75 GPAddrBitsSv39x4: Int = 41, 76 VAddrBitsSv48: Int = 48, 77 GPAddrBitsSv48x4: Int = 50, 78 HasFPU: Boolean = true, 79 HasVPU: Boolean = true, 80 HasCustomCSRCacheOp: Boolean = true, 81 FetchWidth: Int = 8, 82 AsidLength: Int = 16, 83 VmidLength: Int = 14, 84 EnableBPU: Boolean = true, 85 EnableBPD: Boolean = true, 86 EnableRAS: Boolean = true, 87 EnableLB: Boolean = false, 88 EnableLoop: Boolean = true, 89 EnableSC: Boolean = true, 90 EnbaleTlbDebug: Boolean = false, 91 EnableClockGate: Boolean = true, 92 EnableJal: Boolean = false, 93 EnableFauFTB: Boolean = true, 94 EnableSv48: Boolean = true, 95 UbtbGHRLength: Int = 4, 96 // HistoryLength: Int = 512, 97 EnableGHistDiff: Boolean = true, 98 EnableCommitGHistDiff: Boolean = true, 99 UbtbSize: Int = 256, 100 FtbSize: Int = 2048, 101 FtbWays: Int = 4, 102 FtbTagLength: Int = 20, 103 RasSize: Int = 16, 104 RasSpecSize: Int = 32, 105 RasCtrSize: Int = 3, 106 CacheLineSize: Int = 512, 107 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 108 // Sets Hist Tag 109 Seq(( 4096, 8, 8), 110 ( 4096, 13, 8), 111 ( 4096, 32, 8), 112 ( 4096, 119, 8)), 113 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 114 // Sets Hist Tag 115 Seq(( 256, 4, 9), 116 ( 256, 8, 9), 117 ( 512, 13, 9), 118 ( 512, 16, 9), 119 ( 512, 32, 9)), 120 SCNRows: Int = 512, 121 SCNTables: Int = 4, 122 SCCtrBits: Int = 6, 123 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 124 numBr: Int = 2, 125 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 126 (resp_in: BranchPredictionResp, p: Parameters) => { 127 val ftb = Module(new FTB()(p)) 128 val uftb = Module(new FauFTB()(p)) 129 val tage = Module(new Tage_SC()(p)) 130 val ras = Module(new RAS()(p)) 131 val ittage = Module(new ITTage()(p)) 132 val preds = Seq(uftb, tage, ftb, ittage, ras) 133 preds.map(_.io := DontCare) 134 135 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 136 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 137 138 uftb.io.in.bits.resp_in(0) := resp_in 139 tage.io.in.bits.resp_in(0) := uftb.io.out 140 ftb.io.in.bits.resp_in(0) := tage.io.out 141 ittage.io.in.bits.resp_in(0) := ftb.io.out 142 ras.io.in.bits.resp_in(0) := ittage.io.out 143 144 (preds, ras.io.out) 145 }, 146 ICacheForceMetaECCError: Boolean = false, 147 ICacheForceDataECCError: Boolean = false, 148 IBufSize: Int = 48, 149 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 150 DecodeWidth: Int = 6, 151 RenameWidth: Int = 6, 152 CommitWidth: Int = 8, 153 RobCommitWidth: Int = 8, 154 RabCommitWidth: Int = 6, 155 MaxUopSize: Int = 65, 156 EnableRenameSnapshot: Boolean = true, 157 RenameSnapshotNum: Int = 4, 158 FtqSize: Int = 64, 159 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 160 IntLogicRegs: Int = 32, 161 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 162 VecLogicRegs: Int = 32 + 15, // 15: tmp 163 V0LogicRegs: Int = 1, // V0 164 VlLogicRegs: Int = 1, // Vl 165 V0_IDX: Int = 0, 166 Vl_IDX: Int = 0, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 32, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 4, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 56, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 intPreg: PregParams = IntPregParams( 185 numEntries = 224, 186 numRead = None, 187 numWrite = None, 188 ), 189 fpPreg: PregParams = FpPregParams( 190 numEntries = 192, 191 numRead = None, 192 numWrite = None, 193 ), 194 vfPreg: VfPregParams = VfPregParams( 195 numEntries = 128, 196 numRead = None, 197 numWrite = None, 198 ), 199 v0Preg: V0PregParams = V0PregParams( 200 numEntries = 22, 201 numRead = None, 202 numWrite = None, 203 ), 204 vlPreg: VlPregParams = VlPregParams( 205 numEntries = 32, 206 numRead = None, 207 numWrite = None, 208 ), 209 IntRegCacheSize: Int = 16, 210 MemRegCacheSize: Int = 12, 211 intSchdVlWbPort: Int = 0, 212 vfSchdVlWbPort: Int = 1, 213 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 214 IfuRedirectNum: Int = 1, 215 LoadPipelineWidth: Int = 3, 216 StorePipelineWidth: Int = 2, 217 VecLoadPipelineWidth: Int = 2, 218 VecStorePipelineWidth: Int = 2, 219 VecMemSrcInWidth: Int = 2, 220 VecMemInstWbWidth: Int = 1, 221 VecMemDispatchWidth: Int = 1, 222 VecMemDispatchMaxNumber: Int = 16, 223 VecMemUnitStrideMaxFlowNum: Int = 2, 224 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 16, 16, 16, 16, 16), 225 StoreBufferSize: Int = 16, 226 StoreBufferThreshold: Int = 7, 227 EnsbufferWidth: Int = 2, 228 LoadDependencyWidth: Int = 2, 229 // ============ VLSU ============ 230 VlMergeBufferSize: Int = 16, 231 VsMergeBufferSize: Int = 16, 232 UopWritebackWidth: Int = 2, 233 VLUopWritebackWidth: Int = 2, 234 VSUopWritebackWidth: Int = 1, 235 VSegmentBufferSize: Int = 8, 236 VFOFBufferSize: Int = 8, 237 VLFOFWritebackWidth: Int = 1, 238 // ============================== 239 UncacheBufferSize: Int = 4, 240 EnableLoadToLoadForward: Boolean = false, 241 EnableFastForward: Boolean = true, 242 EnableLdVioCheckAfterReset: Boolean = true, 243 EnableSoftPrefetchAfterReset: Boolean = true, 244 EnableCacheErrorAfterReset: Boolean = true, 245 EnableAccurateLoadError: Boolean = false, 246 EnableUncacheWriteOutstanding: Boolean = false, 247 EnableHardwareStoreMisalign: Boolean = true, 248 EnableHardwareLoadMisalign: Boolean = true, 249 EnableStorePrefetchAtIssue: Boolean = false, 250 EnableStorePrefetchAtCommit: Boolean = false, 251 EnableAtCommitMissTrigger: Boolean = true, 252 EnableStorePrefetchSMS: Boolean = false, 253 EnableStorePrefetchSPB: Boolean = false, 254 HasCMO: Boolean = true, 255 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 256 MMUVmidLen: Int = 14, 257 ReSelectLen: Int = 7, // load replay queue replay select counter len 258 iwpuParameters: WPUParameters = WPUParameters( 259 enWPU = false, 260 algoName = "mmru", 261 isICache = true, 262 ), 263 dwpuParameters: WPUParameters = WPUParameters( 264 enWPU = false, 265 algoName = "mmru", 266 enCfPred = false, 267 isICache = false, 268 ), 269 itlbParameters: TLBParameters = TLBParameters( 270 name = "itlb", 271 fetchi = true, 272 useDmode = false, 273 NWays = 48, 274 ), 275 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 276 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 277 ldtlbParameters: TLBParameters = TLBParameters( 278 name = "ldtlb", 279 NWays = 48, 280 outReplace = false, 281 partialStaticPMP = true, 282 outsideRecvFlush = true, 283 saveLevel = false, 284 lgMaxSize = 4 285 ), 286 sttlbParameters: TLBParameters = TLBParameters( 287 name = "sttlb", 288 NWays = 48, 289 outReplace = false, 290 partialStaticPMP = true, 291 outsideRecvFlush = true, 292 saveLevel = false, 293 lgMaxSize = 4 294 ), 295 hytlbParameters: TLBParameters = TLBParameters( 296 name = "hytlb", 297 NWays = 48, 298 outReplace = false, 299 partialStaticPMP = true, 300 outsideRecvFlush = true, 301 saveLevel = false, 302 lgMaxSize = 4 303 ), 304 pftlbParameters: TLBParameters = TLBParameters( 305 name = "pftlb", 306 NWays = 48, 307 outReplace = false, 308 partialStaticPMP = true, 309 outsideRecvFlush = true, 310 saveLevel = false, 311 lgMaxSize = 4 312 ), 313 l2ToL1tlbParameters: TLBParameters = TLBParameters( 314 name = "l2tlb", 315 NWays = 48, 316 outReplace = false, 317 partialStaticPMP = true, 318 outsideRecvFlush = true, 319 saveLevel = false 320 ), 321 refillBothTlb: Boolean = false, 322 btlbParameters: TLBParameters = TLBParameters( 323 name = "btlb", 324 NWays = 48, 325 ), 326 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 327 NumPerfCounters: Int = 16, 328 icacheParameters: ICacheParameters = ICacheParameters( 329 tagECC = Some("parity"), 330 dataECC = Some("parity"), 331 replacer = Some("setplru"), 332 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)) 333 ), 334 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 335 tagECC = Some("secded"), 336 dataECC = Some("secded"), 337 replacer = Some("setplru"), 338 nMissEntries = 16, 339 nProbeEntries = 8, 340 nReleaseEntries = 18, 341 nMaxPrefetchEntry = 6, 342 enableTagEcc = true, 343 enableDataEcc = true, 344 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 345 )), 346 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 347 name = "l2", 348 ways = 8, 349 sets = 1024, // default 512KB L2 350 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 351 coupledL2.prefetch.TPParameters()), 352 )), 353 L2NBanks: Int = 1, 354 usePTWRepeater: Boolean = false, 355 softTLB: Boolean = false, // dpi-c l1tlb debug only 356 softPTW: Boolean = false, // dpi-c l2tlb debug only 357 softPTWDelay: Int = 1, 358 hasMbist:Boolean = false 359){ 360 def ISABase = "rv64i" 361 def ISAExtensions = Seq( 362 // single letter extensions, in canonical order 363 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 364 // multi-letter extensions, sorted alphanumerically 365 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 366 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 367 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 368 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 369 "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", 370 "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", 371 "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", 372 "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", 373 "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 374 ) 375 376 def vlWidth = log2Up(VLEN) + 1 377 378 /** 379 * the minimum element length of vector elements 380 */ 381 val minVecElen: Int = 8 382 383 /** 384 * the maximum number of elements in vector register 385 */ 386 val maxElemPerVreg: Int = VLEN / minVecElen 387 388 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 389 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 390 391 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 392 val RegCacheIdxWidth = log2Up(RegCacheSize) 393 394 val intSchdParams = { 395 implicit val schdType: SchedulerType = IntScheduler() 396 SchdBlockParams(Seq( 397 IssueBlockParams(Seq( 398 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 399 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 400 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 401 IssueBlockParams(Seq( 402 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 403 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 407 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 408 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 409 IssueBlockParams(Seq( 410 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 411 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 412 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 413 ), 414 numPregs = intPreg.numEntries, 415 numDeqOutside = 0, 416 schdType = schdType, 417 rfDataWidth = intPreg.dataCfg.dataWidth, 418 ) 419 } 420 421 val fpSchdParams = { 422 implicit val schdType: SchedulerType = FpScheduler() 423 SchdBlockParams(Seq( 424 IssueBlockParams(Seq( 425 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 426 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 427 ), numEntries = 18, numEnq = 2, numComp = 14), 428 IssueBlockParams(Seq( 429 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 430 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 431 ), numEntries = 18, numEnq = 2, numComp = 14), 432 IssueBlockParams(Seq( 433 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 434 ), numEntries = 18, numEnq = 2, numComp = 14), 435 ), 436 numPregs = fpPreg.numEntries, 437 numDeqOutside = 0, 438 schdType = schdType, 439 rfDataWidth = fpPreg.dataCfg.dataWidth, 440 ) 441 } 442 443 val vfSchdParams = { 444 implicit val schdType: SchedulerType = VfScheduler() 445 SchdBlockParams(Seq( 446 IssueBlockParams(Seq( 447 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 448 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 449 ), numEntries = 16, numEnq = 2, numComp = 12), 450 IssueBlockParams(Seq( 451 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 452 ExeUnitParams("VFEX3", Seq(VfaluCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 453 ), numEntries = 16, numEnq = 2, numComp = 12), 454 IssueBlockParams(Seq( 455 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 456 ), numEntries = 10, numEnq = 2, numComp = 6), 457 ), 458 numPregs = vfPreg.numEntries, 459 numDeqOutside = 0, 460 schdType = schdType, 461 rfDataWidth = vfPreg.dataCfg.dataWidth, 462 ) 463 } 464 465 val memSchdParams = { 466 implicit val schdType: SchedulerType = MemScheduler() 467 val rfDataWidth = 64 468 469 SchdBlockParams(Seq( 470 IssueBlockParams(Seq( 471 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 472 ), numEntries = 16, numEnq = 2, numComp = 12), 473 IssueBlockParams(Seq( 474 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 475 ), numEntries = 16, numEnq = 2, numComp = 12), 476 IssueBlockParams(Seq( 477 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 478 ), numEntries = 16, numEnq = 2, numComp = 12), 479 IssueBlockParams(Seq( 480 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 481 ), numEntries = 16, numEnq = 2, numComp = 12), 482 IssueBlockParams(Seq( 483 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 484 ), numEntries = 16, numEnq = 2, numComp = 12), 485 IssueBlockParams(Seq( 486 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 487 ), numEntries = 16, numEnq = 2, numComp = 12), 488 IssueBlockParams(Seq( 489 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 490 ), numEntries = 16, numEnq = 2, numComp = 12), 491 IssueBlockParams(Seq( 492 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 493 ), numEntries = 16, numEnq = 2, numComp = 12), 494 IssueBlockParams(Seq( 495 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 496 ), numEntries = 16, numEnq = 2, numComp = 12), 497 ), 498 numPregs = intPreg.numEntries max vfPreg.numEntries, 499 numDeqOutside = 0, 500 schdType = schdType, 501 rfDataWidth = rfDataWidth, 502 ) 503 } 504 505 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 506 507 def iqWakeUpParams = { 508 Seq( 509 WakeUpConfig( 510 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 511 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 512 ), 513 // TODO: add load -> fp slow wakeup 514 WakeUpConfig( 515 Seq("FEX0", "FEX2", "FEX4") -> 516 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 517 ), 518 ).flatten 519 } 520 521 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 522 523 val backendParams: BackendParams = backend.BackendParams( 524 Map( 525 IntScheduler() -> intSchdParams, 526 FpScheduler() -> fpSchdParams, 527 VfScheduler() -> vfSchdParams, 528 MemScheduler() -> memSchdParams, 529 ), 530 Seq( 531 intPreg, 532 fpPreg, 533 vfPreg, 534 v0Preg, 535 vlPreg, 536 fakeIntPreg 537 ), 538 iqWakeUpParams, 539 ) 540 541 // Parameters for trace extension. 542 // Trace parameters is useful for XSTOP. 543 val traceParams: TraceParams = new TraceParams( 544 TraceGroupNum = 3, 545 IaddrWidth = GPAddrBitsSv48x4, 546 PrivWidth = 3, 547 ItypeWidth = 4, 548 IlastsizeWidth = 1, 549 ) 550} 551 552case object DebugOptionsKey extends Field[DebugOptions] 553 554case class DebugOptions 555( 556 FPGAPlatform: Boolean = false, 557 ResetGen: Boolean = false, 558 EnableDifftest: Boolean = false, 559 AlwaysBasicDiff: Boolean = true, 560 EnableDebug: Boolean = false, 561 EnablePerfDebug: Boolean = true, 562 PerfLevel: String = "VERBOSE", 563 UseDRAMSim: Boolean = false, 564 EnableConstantin: Boolean = false, 565 EnableChiselDB: Boolean = false, 566 AlwaysBasicDB: Boolean = true, 567 EnableRollingDB: Boolean = false 568) 569 570trait HasXSParameter { 571 572 implicit val p: Parameters 573 574 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 575 def PmemRanges = p(SoCParamsKey).PmemRanges 576 def KeyIDBits = p(CVMParamskey).KeyIDBits 577 final val PageOffsetWidth = 12 578 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 579 580 def coreParams = p(XSCoreParamsKey) 581 def env = p(DebugOptionsKey) 582 583 def ISABase = coreParams.ISABase 584 def ISAExtensions = coreParams.ISAExtensions 585 def XLEN = coreParams.XLEN 586 def VLEN = coreParams.VLEN 587 def ELEN = coreParams.ELEN 588 def HSXLEN = coreParams.HSXLEN 589 val minFLen = 32 590 val fLen = 64 591 def hartIdLen = p(MaxHartIdBits) 592 val xLen = XLEN 593 594 def HasBitmapCheck = coreParams.HasBitmapCheck 595 def HasBitmapCheckDefault = coreParams.HasBitmapCheckDefault 596 def HasMExtension = coreParams.HasMExtension 597 def HasCExtension = coreParams.HasCExtension 598 def HasHExtension = coreParams.HasHExtension 599 def EnableSv48 = coreParams.EnableSv48 600 def HasDiv = coreParams.HasDiv 601 def HasIcache = coreParams.HasICache 602 def HasDcache = coreParams.HasDCache 603 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 604 def PAddrBitsMax = coreParams.PAddrBitsMax 605 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 606 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 607 def GPAddrBits = { 608 if (EnableSv48) 609 coreParams.GPAddrBitsSv48x4 610 else 611 coreParams.GPAddrBitsSv39x4 612 } 613 def VAddrBits = { 614 if (HasHExtension) { 615 if (EnableSv48) 616 coreParams.GPAddrBitsSv48x4 617 else 618 coreParams.GPAddrBitsSv39x4 619 } else { 620 if (EnableSv48) 621 coreParams.VAddrBitsSv48 622 else 623 coreParams.VAddrBitsSv39 624 } 625 } // VAddrBits is Virtual Memory addr bits 626 627 def VAddrMaxBits = { 628 if(EnableSv48) { 629 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 630 } else { 631 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 632 } 633 } 634 635 def AsidLength = coreParams.AsidLength 636 def VmidLength = coreParams.VmidLength 637 def ReSelectLen = coreParams.ReSelectLen 638 def AddrBytes = AddrBits / 8 // unused 639 def DataBits = XLEN 640 def DataBytes = DataBits / 8 641 def QuadWordBits = DataBits * 2 642 def QuadWordBytes = QuadWordBits / 8 643 def VDataBytes = VLEN / 8 644 def HasFPU = coreParams.HasFPU 645 def HasVPU = coreParams.HasVPU 646 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 647 def FetchWidth = coreParams.FetchWidth 648 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 649 def EnableBPU = coreParams.EnableBPU 650 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 651 def EnableRAS = coreParams.EnableRAS 652 def EnableLB = coreParams.EnableLB 653 def EnableLoop = coreParams.EnableLoop 654 def EnableSC = coreParams.EnableSC 655 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 656 def HistoryLength = coreParams.HistoryLength 657 def EnableGHistDiff = coreParams.EnableGHistDiff 658 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 659 def EnableClockGate = coreParams.EnableClockGate 660 def UbtbGHRLength = coreParams.UbtbGHRLength 661 def UbtbSize = coreParams.UbtbSize 662 def EnableFauFTB = coreParams.EnableFauFTB 663 def FtbSize = coreParams.FtbSize 664 def FtbWays = coreParams.FtbWays 665 def FtbTagLength = coreParams.FtbTagLength 666 def RasSize = coreParams.RasSize 667 def RasSpecSize = coreParams.RasSpecSize 668 def RasCtrSize = coreParams.RasCtrSize 669 670 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 671 coreParams.branchPredictor(resp_in, p) 672 } 673 def numBr = coreParams.numBr 674 def TageTableInfos = coreParams.TageTableInfos 675 def TageBanks = coreParams.numBr 676 def SCNRows = coreParams.SCNRows 677 def SCCtrBits = coreParams.SCCtrBits 678 def SCHistLens = coreParams.SCHistLens 679 def SCNTables = coreParams.SCNTables 680 681 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 682 case ((n, cb), h) => (n, cb, h) 683 } 684 def ITTageTableInfos = coreParams.ITTageTableInfos 685 type FoldedHistoryInfo = Tuple2[Int, Int] 686 def foldedGHistInfos = 687 (TageTableInfos.map{ case (nRows, h, t) => 688 if (h > 0) 689 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 690 else 691 Set[FoldedHistoryInfo]() 692 }.reduce(_++_).toSet ++ 693 SCTableInfos.map{ case (nRows, _, h) => 694 if (h > 0) 695 Set((h, min(log2Ceil(nRows/TageBanks), h))) 696 else 697 Set[FoldedHistoryInfo]() 698 }.reduce(_++_).toSet ++ 699 ITTageTableInfos.map{ case (nRows, h, t) => 700 if (h > 0) 701 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 702 else 703 Set[FoldedHistoryInfo]() 704 }.reduce(_++_) ++ 705 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 706 ).toList 707 708 709 710 def CacheLineSize = coreParams.CacheLineSize 711 def CacheLineHalfWord = CacheLineSize / 16 712 def ExtHistoryLength = HistoryLength + 64 713 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 714 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 715 def IBufSize = coreParams.IBufSize 716 def IBufNBank = coreParams.IBufNBank 717 def backendParams: BackendParams = coreParams.backendParams 718 def DecodeWidth = coreParams.DecodeWidth 719 def RenameWidth = coreParams.RenameWidth 720 def CommitWidth = coreParams.CommitWidth 721 def RobCommitWidth = coreParams.RobCommitWidth 722 def RabCommitWidth = coreParams.RabCommitWidth 723 def MaxUopSize = coreParams.MaxUopSize 724 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 725 def RenameSnapshotNum = coreParams.RenameSnapshotNum 726 def FtqSize = coreParams.FtqSize 727 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 728 def IntLogicRegs = coreParams.IntLogicRegs 729 def FpLogicRegs = coreParams.FpLogicRegs 730 def VecLogicRegs = coreParams.VecLogicRegs 731 def V0LogicRegs = coreParams.V0LogicRegs 732 def VlLogicRegs = coreParams.VlLogicRegs 733 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 734 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 735 def V0_IDX = coreParams.V0_IDX 736 def Vl_IDX = coreParams.Vl_IDX 737 def IntPhyRegs = coreParams.intPreg.numEntries 738 def FpPhyRegs = coreParams.fpPreg.numEntries 739 def VfPhyRegs = coreParams.vfPreg.numEntries 740 def V0PhyRegs = coreParams.v0Preg.numEntries 741 def VlPhyRegs = coreParams.vlPreg.numEntries 742 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 743 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 744 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 745 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 746 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 747 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 748 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 749 def RobSize = coreParams.RobSize 750 def RabSize = coreParams.RabSize 751 def VTypeBufferSize = coreParams.VTypeBufferSize 752 def IntRegCacheSize = coreParams.IntRegCacheSize 753 def MemRegCacheSize = coreParams.MemRegCacheSize 754 def RegCacheSize = coreParams.RegCacheSize 755 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 756 /** 757 * the minimum element length of vector elements 758 */ 759 def minVecElen: Int = coreParams.minVecElen 760 761 /** 762 * the maximum number of elements in vector register 763 */ 764 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 765 766 def IntRefCounterWidth = log2Ceil(RobSize) 767 def LSQEnqWidth = RenameWidth 768 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 769 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 770 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 771 def LoadQueueRARSize = coreParams.LoadQueueRARSize 772 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 773 def RollbackGroupSize = coreParams.RollbackGroupSize 774 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 775 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 776 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 777 def StoreQueueSize = coreParams.StoreQueueSize 778 def StoreQueueForceWriteSbufferUpper = coreParams.StoreQueueSize - 4 779 def StoreQueueForceWriteSbufferLower = StoreQueueForceWriteSbufferUpper - 5 780 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 781 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 782 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 783 def VlsQueueSize = coreParams.VlsQueueSize 784 785 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 786 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 787 788 def NumRedirect = backendParams.numRedirect 789 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 790 def FtqRedirectAheadNum = NumRedirect 791 def IfuRedirectNum = coreParams.IfuRedirectNum 792 def LoadPipelineWidth = coreParams.LoadPipelineWidth 793 def StorePipelineWidth = coreParams.StorePipelineWidth 794 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 795 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 796 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 797 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 798 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 799 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 800 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 801 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 802 def StoreBufferSize = coreParams.StoreBufferSize 803 def StoreBufferThreshold = coreParams.StoreBufferThreshold 804 def EnsbufferWidth = coreParams.EnsbufferWidth 805 def LoadDependencyWidth = coreParams.LoadDependencyWidth 806 def VlMergeBufferSize = coreParams.VlMergeBufferSize 807 def VsMergeBufferSize = coreParams.VsMergeBufferSize 808 def UopWritebackWidth = coreParams.UopWritebackWidth 809 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 810 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 811 def VSegmentBufferSize = coreParams.VSegmentBufferSize 812 def VFOFBufferSize = coreParams.VFOFBufferSize 813 def UncacheBufferSize = coreParams.UncacheBufferSize 814 def UncacheBufferIndexWidth = log2Up(UncacheBufferSize) 815 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 816 def EnableFastForward = coreParams.EnableFastForward 817 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 818 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 819 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 820 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 821 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 822 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 823 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 824 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 825 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 826 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 827 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 828 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 829 def HasCMO = coreParams.HasCMO && p(EnableCHI) 830 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 831 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 832 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 833 def asidLen = coreParams.MMUAsidLen 834 def vmidLen = coreParams.MMUVmidLen 835 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 836 def refillBothTlb = coreParams.refillBothTlb 837 def iwpuParam = coreParams.iwpuParameters 838 def dwpuParam = coreParams.dwpuParameters 839 def itlbParams = coreParams.itlbParameters 840 def ldtlbParams = coreParams.ldtlbParameters 841 def sttlbParams = coreParams.sttlbParameters 842 def hytlbParams = coreParams.hytlbParameters 843 def pftlbParams = coreParams.pftlbParameters 844 def l2ToL1Params = coreParams.l2ToL1tlbParameters 845 def btlbParams = coreParams.btlbParameters 846 def l2tlbParams = coreParams.l2tlbParameters 847 def NumPerfCounters = coreParams.NumPerfCounters 848 849 def instBytes = if (HasCExtension) 2 else 4 850 def instOffsetBits = log2Ceil(instBytes) 851 852 def icacheParameters = coreParams.icacheParameters 853 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 854 855 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 856 // for constrained LR/SC loop 857 def LRSCCycles = 64 858 // for lr storm 859 def LRSCBackOff = 8 860 861 // cache hierarchy configurations 862 def l1BusDataWidth = 256 863 864 // load violation predict 865 def ResetTimeMax2Pow = 20 //1078576 866 def ResetTimeMin2Pow = 10 //1024 867 // wait table parameters 868 def WaitTableSize = 1024 869 def MemPredPCWidth = log2Up(WaitTableSize) 870 def LWTUse2BitCounter = true 871 // store set parameters 872 def SSITSize = WaitTableSize 873 def LFSTSize = 32 874 def SSIDWidth = log2Up(LFSTSize) 875 def LFSTWidth = 4 876 def StoreSetEnable = true // LWT will be disabled if SS is enabled 877 def LFSTEnable = true 878 879 def PCntIncrStep: Int = 6 880 def numPCntHc: Int = 12 881 def numPCntPtw: Int = 19 882 883 def numCSRPCntFrontend = 8 884 def numCSRPCntCtrl = 8 885 def numCSRPCntLsu = 8 886 def numCSRPCntHc = 5 887 def printEventCoding = true 888 def printCriticalError = false 889 def maxCommitStuck = pow(2, 21).toInt 890 891 // Vector load exception 892 def maxMergeNumPerCycle = 4 893 894 // Parameters for Sdtrig extension 895 protected def TriggerNum = 4 896 protected def TriggerChainMaxLength = 2 897 898 // Parameters for Trace extension 899 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 900 def CauseWidth = XLEN 901 def TvalWidth = coreParams.traceParams.IaddrWidth 902 def PrivWidth = coreParams.traceParams.PrivWidth 903 def IaddrWidth = coreParams.traceParams.IaddrWidth 904 def ItypeWidth = coreParams.traceParams.ItypeWidth 905 def IretireWidthInPipe = log2Up(RenameWidth * 2) 906 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 907 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 908 909 def hasMbist = coreParams.hasMbist 910} 911