1package xiangshan 2 3import chipsalliance.rocketchip.config.{Field, Parameters} 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.exu._ 7import xiangshan.backend.fu._ 8import xiangshan.backend.fu.fpu._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 11import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 12 13case object XSCoreParamsKey extends Field[XSCoreParameters] 14 15case class XSCoreParameters 16( 17 HasPrefetch: Boolean = false, 18 HartId: Int = 0, 19 XLEN: Int = 64, 20 HasMExtension: Boolean = true, 21 HasCExtension: Boolean = true, 22 HasDiv: Boolean = true, 23 HasICache: Boolean = true, 24 HasDCache: Boolean = true, 25 AddrBits: Int = 64, 26 VAddrBits: Int = 39, 27 PAddrBits: Int = 40, 28 HasFPU: Boolean = true, 29 FetchWidth: Int = 8, 30 EnableBPU: Boolean = true, 31 EnableBPD: Boolean = true, 32 EnableRAS: Boolean = true, 33 EnableLB: Boolean = false, 34 EnableLoop: Boolean = true, 35 EnableSC: Boolean = true, 36 EnbaleTlbDebug: Boolean = false, 37 EnableJal: Boolean = false, 38 EnableUBTB: Boolean = true, 39 HistoryLength: Int = 64, 40 BtbSize: Int = 2048, 41 JbtacSize: Int = 1024, 42 JbtacBanks: Int = 8, 43 RasSize: Int = 16, 44 CacheLineSize: Int = 512, 45 UBtbWays: Int = 16, 46 BtbWays: Int = 2, 47 48 EnableL1plusPrefetcher: Boolean = true, 49 IBufSize: Int = 48, 50 DecodeWidth: Int = 6, 51 RenameWidth: Int = 6, 52 CommitWidth: Int = 6, 53 BrqSize: Int = 32, 54 FtqSize: Int = 48, 55 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 56 IssQueSize: Int = 16, 57 NRPhyRegs: Int = 160, 58 NRIntReadPorts: Int = 14, 59 NRIntWritePorts: Int = 8, 60 NRFpReadPorts: Int = 14, 61 NRFpWritePorts: Int = 8, 62 LoadQueueSize: Int = 64, 63 StoreQueueSize: Int = 48, 64 RoqSize: Int = 192, 65 dpParams: DispatchParameters = DispatchParameters( 66 IntDqSize = 16, 67 FpDqSize = 16, 68 LsDqSize = 16, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4 72 ), 73 exuParameters: ExuParameters = ExuParameters( 74 JmpCnt = 1, 75 AluCnt = 4, 76 MulCnt = 0, 77 MduCnt = 2, 78 FmacCnt = 4, 79 FmiscCnt = 2, 80 FmiscDivSqrtCnt = 0, 81 LduCnt = 2, 82 StuCnt = 2 83 ), 84 LoadPipelineWidth: Int = 2, 85 StorePipelineWidth: Int = 2, 86 StoreBufferSize: Int = 16, 87 RefillSize: Int = 512, 88 TlbEntrySize: Int = 32, 89 TlbSPEntrySize: Int = 4, 90 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 91 PtwSPEntrySize: Int = 16, 92 PtwL1EntrySize: Int = 16, 93 PtwL2EntrySize: Int = 2048, //(256 * 8) 94 NumPerfCounters: Int = 16, 95 useFakePTW: Boolean = false, 96 useFakeDCache: Boolean = false, 97 useFakeL1plusCache: Boolean = false 98){ 99 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 100 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 101 102 val intExuConfigs = JumpExeUnitCfg +: ( 103 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++ 104 Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) 105 ) 106 107 val fpExuConfigs = 108 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 109 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 110 111 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 112} 113 114case object DebugOptionsKey extends Field[DebugOptions] 115 116case class DebugOptions 117( 118 FPGAPlatform: Boolean = true, 119 EnableDebug: Boolean = true, 120 EnablePerfDebug: Boolean = true, 121 UseDRAMSim: Boolean = false 122) 123 124trait HasXSParameter { 125 126 implicit val p: Parameters 127 128 val coreParams = p(XSCoreParamsKey) 129 val env = p(DebugOptionsKey) 130 131 val XLEN = coreParams.XLEN 132 val hardId = coreParams.HartId 133 val minFLen = 32 134 val fLen = 64 135 def xLen = XLEN 136 137 val HasMExtension = coreParams.HasMExtension 138 val HasCExtension = coreParams.HasCExtension 139 val HasDiv = coreParams.HasDiv 140 val HasIcache = coreParams.HasICache 141 val HasDcache = coreParams.HasDCache 142 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 143 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 144 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 145 val AddrBytes = AddrBits / 8 // unused 146 val DataBits = XLEN 147 val DataBytes = DataBits / 8 148 val HasFPU = coreParams.HasFPU 149 val FetchWidth = coreParams.FetchWidth 150 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 151 val EnableBPU = coreParams.EnableBPU 152 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 153 val EnableRAS = coreParams.EnableRAS 154 val EnableLB = coreParams.EnableLB 155 val EnableLoop = coreParams.EnableLoop 156 val EnableSC = coreParams.EnableSC 157 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 158 val HistoryLength = coreParams.HistoryLength 159 val BtbSize = coreParams.BtbSize 160 // val BtbWays = 4 161 val BtbBanks = PredictWidth 162 // val BtbSets = BtbSize / BtbWays 163 val JbtacSize = coreParams.JbtacSize 164 val JbtacBanks = coreParams.JbtacBanks 165 val RasSize = coreParams.RasSize 166 val CacheLineSize = coreParams.CacheLineSize 167 val CacheLineHalfWord = CacheLineSize / 16 168 val ExtHistoryLength = HistoryLength + 64 169 val UBtbWays = coreParams.UBtbWays 170 val BtbWays = coreParams.BtbWays 171 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 172 val IBufSize = coreParams.IBufSize 173 val DecodeWidth = coreParams.DecodeWidth 174 val RenameWidth = coreParams.RenameWidth 175 val CommitWidth = coreParams.CommitWidth 176 val BrqSize = coreParams.BrqSize 177 val FtqSize = coreParams.FtqSize 178 val IssQueSize = coreParams.IssQueSize 179 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 180 val BrTagWidth = log2Up(BrqSize) 181 val NRPhyRegs = coreParams.NRPhyRegs 182 val PhyRegIdxWidth = log2Up(NRPhyRegs) 183 val RoqSize = coreParams.RoqSize 184 val LoadQueueSize = coreParams.LoadQueueSize 185 val StoreQueueSize = coreParams.StoreQueueSize 186 val dpParams = coreParams.dpParams 187 val exuParameters = coreParams.exuParameters 188 val NRIntReadPorts = coreParams.NRIntReadPorts 189 val NRIntWritePorts = coreParams.NRIntWritePorts 190 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 191 val NRFpReadPorts = coreParams.NRFpReadPorts 192 val NRFpWritePorts = coreParams.NRFpWritePorts 193 val LoadPipelineWidth = coreParams.LoadPipelineWidth 194 val StorePipelineWidth = coreParams.StorePipelineWidth 195 val StoreBufferSize = coreParams.StoreBufferSize 196 val RefillSize = coreParams.RefillSize 197 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 198 val TlbEntrySize = coreParams.TlbEntrySize 199 val TlbSPEntrySize = coreParams.TlbSPEntrySize 200 val PtwL3EntrySize = coreParams.PtwL3EntrySize 201 val PtwSPEntrySize = coreParams.PtwSPEntrySize 202 val PtwL1EntrySize = coreParams.PtwL1EntrySize 203 val PtwL2EntrySize = coreParams.PtwL2EntrySize 204 val NumPerfCounters = coreParams.NumPerfCounters 205 206 val instBytes = if (HasCExtension) 2 else 4 207 val instOffsetBits = log2Ceil(instBytes) 208 209 val icacheParameters = ICacheParameters( 210 tagECC = Some("parity"), 211 dataECC = Some("parity"), 212 replacer = Some("setplru"), 213 nMissEntries = 2 214 ) 215 216 val l1plusCacheParameters = L1plusCacheParameters( 217 tagECC = Some("secded"), 218 dataECC = Some("secded"), 219 replacer = Some("setplru"), 220 nMissEntries = 8 221 ) 222 223 val dcacheParameters = DCacheParameters( 224 tagECC = Some("secded"), 225 dataECC = Some("secded"), 226 replacer = Some("setplru"), 227 nMissEntries = 16, 228 nProbeEntries = 16, 229 nReleaseEntries = 16, 230 nStoreReplayEntries = 16 231 ) 232 233 val LRSCCycles = 100 234 235 236 // cache hierarchy configurations 237 val l1BusDataWidth = 256 238 239 val useFakeDCache = coreParams.useFakeDCache 240 val useFakePTW = coreParams.useFakePTW 241 val useFakeL1plusCache = coreParams.useFakeL1plusCache 242 // L2 configurations 243 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache 244 val L1BusWidth = 256 245 val L2Size = 512 * 1024 // 512KB 246 val L2BlockSize = 64 247 val L2NWays = 8 248 val L2NSets = L2Size / L2BlockSize / L2NWays 249 250 // L3 configurations 251 val L2BusWidth = 256 252 253 // icache prefetcher 254 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 255 enable = true, 256 _type = "stream", 257 streamParams = StreamPrefetchParameters( 258 streamCnt = 2, 259 streamSize = 4, 260 ageWidth = 4, 261 blockBytes = l1plusCacheParameters.blockBytes, 262 reallocStreamOnMissInstantly = true, 263 cacheName = "icache" 264 ) 265 ) 266 267 // dcache prefetcher 268 val l2PrefetcherParameters = L2PrefetcherParameters( 269 enable = true, 270 _type = "bop", // "stream" or "bop" 271 streamParams = StreamPrefetchParameters( 272 streamCnt = 4, 273 streamSize = 4, 274 ageWidth = 4, 275 blockBytes = L2BlockSize, 276 reallocStreamOnMissInstantly = true, 277 cacheName = "dcache" 278 ), 279 bopParams = BOPParameters( 280 rrTableEntries = 256, 281 rrTagBits = 12, 282 scoreBits = 5, 283 roundMax = 50, 284 badScore = 1, 285 blockBytes = L2BlockSize, 286 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 287 ), 288 ) 289 290 val loadExuConfigs = coreParams.loadExuConfigs 291 val storeExuConfigs = coreParams.storeExuConfigs 292 293 val intExuConfigs = coreParams.intExuConfigs 294 295 val fpExuConfigs = coreParams.fpExuConfigs 296 297 val exuConfigs = coreParams.exuConfigs 298 299} 300