1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 PathHistoryLength: Int = 16, 59 BtbSize: Int = 2048, 60 JbtacSize: Int = 1024, 61 JbtacBanks: Int = 8, 62 RasSize: Int = 32, 63 CacheLineSize: Int = 512, 64 UBtbWays: Int = 16, 65 BtbWays: Int = 2, 66 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 67 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 68 // val loop = Module(new LoopPredictor) 69 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 70 // else Module(new Tage) } 71 // else { Module(new FakeTage) }) 72 val ftb = Module(new FTB()(p)) 73 val ubtb = Module(new MicroBTB()(p)) 74 val bim = Module(new BIM()(p)) 75 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 76 val ras = Module(new RAS()(p)) 77 val ittage = Module(new ITTage()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 95 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 96 97 (preds, ras.io.out.resp) 98 }), 99 IBufSize: Int = 48, 100 DecodeWidth: Int = 6, 101 RenameWidth: Int = 6, 102 CommitWidth: Int = 6, 103 FtqSize: Int = 64, 104 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 105 IssQueSize: Int = 16, 106 NRPhyRegs: Int = 192, 107 NRIntReadPorts: Int = 14, 108 NRIntWritePorts: Int = 8, 109 NRFpReadPorts: Int = 14, 110 NRFpWritePorts: Int = 8, 111 LoadQueueSize: Int = 80, 112 StoreQueueSize: Int = 64, 113 RobSize: Int = 256, 114 EnableIntMoveElim: Boolean = true, 115 IntRefCounterWidth: Int = 2, 116 dpParams: DispatchParameters = DispatchParameters( 117 IntDqSize = 16, 118 FpDqSize = 16, 119 LsDqSize = 16, 120 IntDqDeqWidth = 4, 121 FpDqDeqWidth = 4, 122 LsDqDeqWidth = 4 123 ), 124 exuParameters: ExuParameters = ExuParameters( 125 JmpCnt = 1, 126 AluCnt = 4, 127 MulCnt = 0, 128 MduCnt = 2, 129 FmacCnt = 4, 130 FmiscCnt = 2, 131 FmiscDivSqrtCnt = 0, 132 LduCnt = 2, 133 StuCnt = 2 134 ), 135 LoadPipelineWidth: Int = 2, 136 StorePipelineWidth: Int = 2, 137 StoreBufferSize: Int = 16, 138 StoreBufferThreshold: Int = 7, 139 EnableFastForward: Boolean = true, 140 RefillSize: Int = 512, 141 itlbParameters: TLBParameters = TLBParameters( 142 name = "itlb", 143 fetchi = true, 144 useDmode = false, 145 sameCycle = true, 146 normalNWays = 32, 147 normalReplacer = Some("plru"), 148 superNWays = 4, 149 superReplacer = Some("plru"), 150 shouldBlock = true 151 ), 152 ldtlbParameters: TLBParameters = TLBParameters( 153 name = "ldtlb", 154 normalNSets = 128, 155 normalNWays = 1, 156 normalAssociative = "sa", 157 normalReplacer = Some("setplru"), 158 superNWays = 8, 159 normalAsVictim = true, 160 outReplace = true 161 ), 162 sttlbParameters: TLBParameters = TLBParameters( 163 name = "sttlb", 164 normalNSets = 128, 165 normalNWays = 1, 166 normalAssociative = "sa", 167 normalReplacer = Some("setplru"), 168 superNWays = 8, 169 normalAsVictim = true, 170 outReplace = true 171 ), 172 refillBothTlb: Boolean = false, 173 btlbParameters: TLBParameters = TLBParameters( 174 name = "btlb", 175 normalNSets = 1, 176 normalNWays = 64, 177 superNWays = 4, 178 ), 179 useBTlb: Boolean = false, 180 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 181 NumPerfCounters: Int = 16, 182 icacheParameters: ICacheParameters = ICacheParameters( 183 tagECC = Some("parity"), 184 dataECC = Some("parity"), 185 replacer = Some("setplru"), 186 nMissEntries = 2 187 ), 188 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 189 tagECC = Some("secded"), 190 dataECC = Some("secded"), 191 replacer = Some("setplru"), 192 nMissEntries = 16, 193 nProbeEntries = 16, 194 nReleaseEntries = 16, 195 nStoreReplayEntries = 16 196 )), 197 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 198 name = "l2", 199 level = 2, 200 ways = 8, 201 sets = 1024, // default 512KB L2 202 prefetch = Some(huancun.prefetch.BOPParameters()) 203 )), 204 L2NBanks: Int = 1, 205 usePTWRepeater: Boolean = false, 206 softPTW: Boolean = false // dpi-c debug only 207){ 208 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 209 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 210 211 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 212 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 213 214 val fpExuConfigs = 215 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 216 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 217 218 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 219} 220 221case object DebugOptionsKey extends Field[DebugOptions] 222 223case class DebugOptions 224( 225 FPGAPlatform: Boolean = true, 226 EnableDebug: Boolean = true, 227 EnablePerfDebug: Boolean = true, 228 UseDRAMSim: Boolean = false 229) 230 231trait HasXSParameter { 232 233 implicit val p: Parameters 234 235 val coreParams = p(XSCoreParamsKey) 236 val env = p(DebugOptionsKey) 237 238 val XLEN = coreParams.XLEN 239 val hardId = coreParams.HartId 240 val minFLen = 32 241 val fLen = 64 242 def xLen = XLEN 243 244 val HasMExtension = coreParams.HasMExtension 245 val HasCExtension = coreParams.HasCExtension 246 val HasDiv = coreParams.HasDiv 247 val HasIcache = coreParams.HasICache 248 val HasDcache = coreParams.HasDCache 249 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 250 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 251 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 252 val AddrBytes = AddrBits / 8 // unused 253 val DataBits = XLEN 254 val DataBytes = DataBits / 8 255 val HasFPU = coreParams.HasFPU 256 val FetchWidth = coreParams.FetchWidth 257 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 258 val EnableBPU = coreParams.EnableBPU 259 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 260 val EnableRAS = coreParams.EnableRAS 261 val EnableLB = coreParams.EnableLB 262 val EnableLoop = coreParams.EnableLoop 263 val EnableSC = coreParams.EnableSC 264 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 265 val HistoryLength = coreParams.HistoryLength 266 val PathHistoryLength = coreParams.PathHistoryLength 267 val BtbSize = coreParams.BtbSize 268 // val BtbWays = 4 269 val BtbBanks = PredictWidth 270 // val BtbSets = BtbSize / BtbWays 271 val JbtacSize = coreParams.JbtacSize 272 val JbtacBanks = coreParams.JbtacBanks 273 val RasSize = coreParams.RasSize 274 275 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 276 coreParams.branchPredictor(resp_in, p, enableSC) 277 } 278 279 val CacheLineSize = coreParams.CacheLineSize 280 val CacheLineHalfWord = CacheLineSize / 16 281 val ExtHistoryLength = HistoryLength + 64 282 val UBtbWays = coreParams.UBtbWays 283 val BtbWays = coreParams.BtbWays 284 val IBufSize = coreParams.IBufSize 285 val DecodeWidth = coreParams.DecodeWidth 286 val RenameWidth = coreParams.RenameWidth 287 val CommitWidth = coreParams.CommitWidth 288 val FtqSize = coreParams.FtqSize 289 val IssQueSize = coreParams.IssQueSize 290 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 291 val NRPhyRegs = coreParams.NRPhyRegs 292 val PhyRegIdxWidth = log2Up(NRPhyRegs) 293 val RobSize = coreParams.RobSize 294 val EnableIntMoveElim = coreParams.EnableIntMoveElim 295 val IntRefCounterWidth = coreParams.IntRefCounterWidth 296 val StdFreeListSize = NRPhyRegs - 32 297 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 298 val MEFreeListSize = NRPhyRegs 299 val LoadQueueSize = coreParams.LoadQueueSize 300 val StoreQueueSize = coreParams.StoreQueueSize 301 val dpParams = coreParams.dpParams 302 val exuParameters = coreParams.exuParameters 303 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 304 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 305 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 306 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 307 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 308 val LoadPipelineWidth = coreParams.LoadPipelineWidth 309 val StorePipelineWidth = coreParams.StorePipelineWidth 310 val StoreBufferSize = coreParams.StoreBufferSize 311 val StoreBufferThreshold = coreParams.StoreBufferThreshold 312 val EnableFastForward = coreParams.EnableFastForward 313 val RefillSize = coreParams.RefillSize 314 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 315 val refillBothTlb = coreParams.refillBothTlb 316 val useBTlb = coreParams.useBTlb 317 val itlbParams = coreParams.itlbParameters 318 val ldtlbParams = coreParams.ldtlbParameters 319 val sttlbParams = coreParams.sttlbParameters 320 val btlbParams = coreParams.btlbParameters 321 val l2tlbParams = coreParams.l2tlbParameters 322 val NumPerfCounters = coreParams.NumPerfCounters 323 324 val instBytes = if (HasCExtension) 2 else 4 325 val instOffsetBits = log2Ceil(instBytes) 326 327 val icacheParameters = coreParams.icacheParameters 328 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 329 330 val LRSCCycles = 100 331 332 // cache hierarchy configurations 333 val l1BusDataWidth = 256 334 335 // load violation predict 336 val ResetTimeMax2Pow = 20 //1078576 337 val ResetTimeMin2Pow = 10 //1024 338 // wait table parameters 339 val WaitTableSize = 1024 340 val MemPredPCWidth = log2Up(WaitTableSize) 341 val LWTUse2BitCounter = true 342 // store set parameters 343 val SSITSize = WaitTableSize 344 val LFSTSize = 32 345 val SSIDWidth = log2Up(LFSTSize) 346 val LFSTWidth = 4 347 val StoreSetEnable = true // LWT will be disabled if SS is enabled 348 349 val loadExuConfigs = coreParams.loadExuConfigs 350 val storeExuConfigs = coreParams.storeExuConfigs 351 352 val intExuConfigs = coreParams.intExuConfigs 353 354 val fpExuConfigs = coreParams.fpExuConfigs 355 356 val exuConfigs = coreParams.exuConfigs 357 358} 359