1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.backend.datapath.WakeUpConfig 46import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 47 48import scala.math.min 49 50case object XSTileKey extends Field[Seq[XSCoreParameters]] 51 52case object XSCoreParamsKey extends Field[XSCoreParameters] 53 54case class XSCoreParameters 55( 56 HasPrefetch: Boolean = false, 57 HartId: Int = 0, 58 XLEN: Int = 64, 59 VLEN: Int = 128, 60 ELEN: Int = 64, 61 HasMExtension: Boolean = true, 62 HasCExtension: Boolean = true, 63 HasDiv: Boolean = true, 64 HasICache: Boolean = true, 65 HasDCache: Boolean = true, 66 AddrBits: Int = 64, 67 VAddrBits: Int = 39, 68 HasFPU: Boolean = true, 69 HasVPU: Boolean = true, 70 HasCustomCSRCacheOp: Boolean = true, 71 FetchWidth: Int = 8, 72 AsidLength: Int = 16, 73 EnableBPU: Boolean = true, 74 EnableBPD: Boolean = true, 75 EnableRAS: Boolean = true, 76 EnableLB: Boolean = false, 77 EnableLoop: Boolean = true, 78 EnableSC: Boolean = true, 79 EnbaleTlbDebug: Boolean = false, 80 EnableJal: Boolean = false, 81 EnableFauFTB: Boolean = true, 82 UbtbGHRLength: Int = 4, 83 // HistoryLength: Int = 512, 84 EnableGHistDiff: Boolean = true, 85 EnableCommitGHistDiff: Boolean = true, 86 UbtbSize: Int = 256, 87 FtbSize: Int = 2048, 88 RasSize: Int = 32, 89 CacheLineSize: Int = 512, 90 FtbWays: Int = 4, 91 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 92 // Sets Hist Tag 93 // Seq(( 2048, 2, 8), 94 // ( 2048, 9, 8), 95 // ( 2048, 13, 8), 96 // ( 2048, 20, 8), 97 // ( 2048, 26, 8), 98 // ( 2048, 44, 8), 99 // ( 2048, 73, 8), 100 // ( 2048, 256, 8)), 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 118 ((resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val ubtb =Module(new FauFTB()(p)) 121 // val bim = Module(new BIM()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(ubtb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 // ubtb.io.resp_in(0) := resp_in 129 // bim.io.resp_in(0) := ubtb.io.resp 130 // btb.io.resp_in(0) := bim.io.resp 131 // tage.io.resp_in(0) := btb.io.resp 132 // loop.io.resp_in(0) := tage.io.resp 133 ubtb.io.in.bits.resp_in(0) := resp_in 134 tage.io.in.bits.resp_in(0) := ubtb.io.out 135 ftb.io.in.bits.resp_in(0) := tage.io.out 136 ittage.io.in.bits.resp_in(0) := ftb.io.out 137 ras.io.in.bits.resp_in(0) := ittage.io.out 138 139 (preds, ras.io.out) 140 }), 141 IBufSize: Int = 48, 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 6, 145 MaxUopSize: Int = 65, 146 FtqSize: Int = 64, 147 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 148 IntLogicRegs: Int = 32, 149 FpLogicRegs: Int = 33, 150 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 151 VCONFIG_IDX: Int = 32, 152 NRPhyRegs: Int = 192, 153 VirtualLoadQueueSize: Int = 80, 154 LoadQueueRARSize: Int = 80, 155 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 156 RollbackGroupSize: Int = 8, 157 LoadQueueReplaySize: Int = 80, 158 LoadUncacheBufferSize: Int = 20, 159 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 160 StoreQueueSize: Int = 64, 161 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 162 StoreQueueForwardWithMask: Boolean = true, 163 VlsQueueSize: Int = 8, 164 RobSize: Int = 256, 165 RabSize: Int = 256, 166 dpParams: DispatchParameters = DispatchParameters( 167 IntDqSize = 16, 168 FpDqSize = 16, 169 LsDqSize = 16, 170 IntDqDeqWidth = 6, 171 FpDqDeqWidth = 6, 172 LsDqDeqWidth = 6, 173 ), 174 intPreg: PregParams = IntPregParams( 175 numEntries = 192, 176 numRead = None, 177 numWrite = None, 178 ), 179 vfPreg: VfPregParams = VfPregParams( 180 numEntries = 192, 181 numRead = None, 182 numWrite = None, 183 ), 184 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 185 LoadPipelineWidth: Int = 2, 186 StorePipelineWidth: Int = 2, 187 VecMemSrcInWidth: Int = 2, 188 VecMemInstWbWidth: Int = 1, 189 VecMemDispatchWidth: Int = 1, 190 StoreBufferSize: Int = 16, 191 StoreBufferThreshold: Int = 7, 192 EnsbufferWidth: Int = 2, 193 UncacheBufferSize: Int = 4, 194 EnableLoadToLoadForward: Boolean = true, 195 EnableFastForward: Boolean = false, 196 EnableLdVioCheckAfterReset: Boolean = true, 197 EnableSoftPrefetchAfterReset: Boolean = true, 198 EnableCacheErrorAfterReset: Boolean = true, 199 EnableDCacheWPU: Boolean = false, 200 EnableAccurateLoadError: Boolean = true, 201 EnableUncacheWriteOutstanding: Boolean = false, 202 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 203 ReSelectLen: Int = 7, // load replay queue replay select counter len 204 itlbParameters: TLBParameters = TLBParameters( 205 name = "itlb", 206 fetchi = true, 207 useDmode = false, 208 normalNWays = 32, 209 normalReplacer = Some("plru"), 210 superNWays = 4, 211 superReplacer = Some("plru") 212 ), 213 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 214 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ldtlbParameters: TLBParameters = TLBParameters( 216 name = "ldtlb", 217 normalNSets = 64, 218 normalNWays = 1, 219 normalAssociative = "sa", 220 normalReplacer = Some("setplru"), 221 superNWays = 16, 222 normalAsVictim = true, 223 outReplace = false, 224 partialStaticPMP = true, 225 outsideRecvFlush = true, 226 saveLevel = true 227 ), 228 sttlbParameters: TLBParameters = TLBParameters( 229 name = "sttlb", 230 normalNSets = 64, 231 normalNWays = 1, 232 normalAssociative = "sa", 233 normalReplacer = Some("setplru"), 234 superNWays = 16, 235 normalAsVictim = true, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 pftlbParameters: TLBParameters = TLBParameters( 242 name = "pftlb", 243 normalNSets = 64, 244 normalNWays = 1, 245 normalAssociative = "sa", 246 normalReplacer = Some("setplru"), 247 superNWays = 16, 248 normalAsVictim = true, 249 outReplace = false, 250 partialStaticPMP = true, 251 outsideRecvFlush = true, 252 saveLevel = true 253 ), 254 refillBothTlb: Boolean = false, 255 btlbParameters: TLBParameters = TLBParameters( 256 name = "btlb", 257 normalNSets = 1, 258 normalNWays = 64, 259 superNWays = 4, 260 ), 261 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 262 NumPerfCounters: Int = 16, 263 icacheParameters: ICacheParameters = ICacheParameters( 264 tagECC = Some("parity"), 265 dataECC = Some("parity"), 266 replacer = Some("setplru"), 267 nMissEntries = 2, 268 nProbeEntries = 2, 269 nPrefetchEntries = 12, 270 nPrefBufferEntries = 64, 271 hasPrefetch = true, 272 ), 273 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 274 tagECC = Some("secded"), 275 dataECC = Some("secded"), 276 replacer = Some("setplru"), 277 nMissEntries = 16, 278 nProbeEntries = 8, 279 nReleaseEntries = 18 280 )), 281 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 282 name = "l2", 283 ways = 8, 284 sets = 1024, // default 512KB L2 285 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 286 )), 287 L2NBanks: Int = 1, 288 usePTWRepeater: Boolean = false, 289 softTLB: Boolean = false, // dpi-c l1tlb debug only 290 softPTW: Boolean = false, // dpi-c l2tlb debug only 291 softPTWDelay: Int = 1 292){ 293 def vlWidth = log2Up(VLEN) + 1 294 295 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 296 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 297 298 val intSchdParams = { 299 implicit val schdType: SchedulerType = IntScheduler() 300 SchdBlockParams(Seq( 301 IssueBlockParams(Seq( 302 ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 303 ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 304 ), numEntries = 8, numEnq = 2), 305 IssueBlockParams(Seq( 306 ExeUnitParams("IEX2", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 307 ExeUnitParams("IEX3", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 308 ), numEntries = 8, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 311 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 312 ), numEntries = 8, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 315 ), numEntries = 8, numEnq = 2), 316 IssueBlockParams(Seq( 317 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 318 ), numEntries = 8, numEnq = 2), 319 ), 320 numPregs = intPreg.numEntries, 321 numDeqOutside = 0, 322 schdType = schdType, 323 rfDataWidth = intPreg.dataCfg.dataWidth, 324 numUopIn = dpParams.IntDqDeqWidth, 325 ) 326 } 327 val vfSchdParams = { 328 implicit val schdType: SchedulerType = VfScheduler() 329 SchdBlockParams(Seq( 330 IssueBlockParams(Seq( 331 ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))), 332 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))), 333 ), numEntries = 8, numEnq = 2), 334 IssueBlockParams(Seq( 335 ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))), 336 ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 3, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))), 337 ), numEntries = 8, numEnq = 2), 338 IssueBlockParams(Seq( 339 ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 340 ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 341 ), numEntries = 8, numEnq = 2), 342 IssueBlockParams(Seq( 343 ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 344 ), numEntries = 8, numEnq = 2), 345 ), 346 numPregs = vfPreg.numEntries, 347 numDeqOutside = 0, 348 schdType = schdType, 349 rfDataWidth = vfPreg.dataCfg.dataWidth, 350 numUopIn = dpParams.FpDqDeqWidth, 351 ) 352 } 353 354 val memSchdParams = { 355 implicit val schdType: SchedulerType = MemScheduler() 356 val rfDataWidth = 64 357 358 SchdBlockParams(Seq( 359 IssueBlockParams(Seq( 360 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 361 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 362 ), numEntries = 8, numEnq = 2), 363 IssueBlockParams(Seq( 364 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))), 365 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))), 366 ), numEntries = 8, numEnq = 2), 367 IssueBlockParams(Seq( 368 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 369 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 370 ), numEntries = 8, numEnq = 2), 371 IssueBlockParams(Seq( 372 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 373 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 374 ), numEntries = 8, numEnq = 2), 375 ), 376 numPregs = intPreg.numEntries max vfPreg.numEntries, 377 numDeqOutside = 0, 378 schdType = schdType, 379 rfDataWidth = rfDataWidth, 380 numUopIn = dpParams.LsDqDeqWidth, 381 ) 382 } 383 384 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 385 386 def iqWakeUpParams = { 387 Seq( 388 WakeUpConfig("IEX0" -> "IEX0"), 389 WakeUpConfig("IEX0" -> "IEX1"), 390 WakeUpConfig("IEX1" -> "IEX0"), 391 WakeUpConfig("IEX1" -> "IEX1"), 392 WakeUpConfig("IEX0" -> "BJU0"), 393 WakeUpConfig("IEX0" -> "BJU1"), 394 WakeUpConfig("IEX1" -> "BJU0"), 395 WakeUpConfig("IEX1" -> "BJU1"), 396 WakeUpConfig("IEX0" -> "LDU0"), 397 WakeUpConfig("IEX0" -> "LDU1"), 398 WakeUpConfig("IEX1" -> "LDU0"), 399 WakeUpConfig("IEX1" -> "LDU1"), 400 WakeUpConfig("IEX0" -> "STA0"), 401 WakeUpConfig("IEX0" -> "STA1"), 402 WakeUpConfig("IEX1" -> "STA0"), 403 WakeUpConfig("IEX1" -> "STA1"), 404 WakeUpConfig("IMISC0" -> "FEX0"), 405 WakeUpConfig("IMISC0" -> "FEX1"), 406 WakeUpConfig("IMISC0" -> "FEX2"), 407 WakeUpConfig("IMISC0" -> "FEX3"), 408 WakeUpConfig("IMISC0" -> "FEX4"), 409 WakeUpConfig("FEX3" -> "FEX0"), 410 WakeUpConfig("FEX3" -> "FEX1"), 411 WakeUpConfig("FEX3" -> "FEX2"), 412 WakeUpConfig("FEX3" -> "FEX3"), 413 ) 414 } 415 416 def backendParams: BackendParams = backend.BackendParams( 417 Map( 418 IntScheduler() -> intSchdParams, 419 VfScheduler() -> vfSchdParams, 420 MemScheduler() -> memSchdParams, 421 ), 422 Seq( 423 intPreg, 424 vfPreg, 425 ), 426 iqWakeUpParams, 427 ) 428} 429 430case object DebugOptionsKey extends Field[DebugOptions] 431 432case class DebugOptions 433( 434 FPGAPlatform: Boolean = false, 435 EnableDifftest: Boolean = false, 436 AlwaysBasicDiff: Boolean = true, 437 EnableDebug: Boolean = false, 438 EnablePerfDebug: Boolean = true, 439 UseDRAMSim: Boolean = false, 440 EnableConstantin: Boolean = false, 441 EnableTopDown: Boolean = false 442) 443 444trait HasXSParameter { 445 446 implicit val p: Parameters 447 448 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 449 450 val coreParams = p(XSCoreParamsKey) 451 val env = p(DebugOptionsKey) 452 453 val XLEN = coreParams.XLEN 454 val VLEN = coreParams.VLEN 455 val ELEN = coreParams.ELEN 456 val minFLen = 32 457 val fLen = 64 458 def xLen = XLEN 459 460 val HasMExtension = coreParams.HasMExtension 461 val HasCExtension = coreParams.HasCExtension 462 val HasDiv = coreParams.HasDiv 463 val HasIcache = coreParams.HasICache 464 val HasDcache = coreParams.HasDCache 465 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 466 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 467 val AsidLength = coreParams.AsidLength 468 val ReSelectLen = coreParams.ReSelectLen 469 val AddrBytes = AddrBits / 8 // unused 470 val DataBits = XLEN 471 val DataBytes = DataBits / 8 472 val HasFPU = coreParams.HasFPU 473 val HasVPU = coreParams.HasVPU 474 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 475 val FetchWidth = coreParams.FetchWidth 476 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 477 val EnableBPU = coreParams.EnableBPU 478 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 479 val EnableRAS = coreParams.EnableRAS 480 val EnableLB = coreParams.EnableLB 481 val EnableLoop = coreParams.EnableLoop 482 val EnableSC = coreParams.EnableSC 483 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 484 val HistoryLength = coreParams.HistoryLength 485 val EnableGHistDiff = coreParams.EnableGHistDiff 486 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 487 val UbtbGHRLength = coreParams.UbtbGHRLength 488 val UbtbSize = coreParams.UbtbSize 489 val EnableFauFTB = coreParams.EnableFauFTB 490 val FtbSize = coreParams.FtbSize 491 val FtbWays = coreParams.FtbWays 492 val RasSize = coreParams.RasSize 493 494 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 495 coreParams.branchPredictor(resp_in, p) 496 } 497 val numBr = coreParams.numBr 498 val TageTableInfos = coreParams.TageTableInfos 499 val TageBanks = coreParams.numBr 500 val SCNRows = coreParams.SCNRows 501 val SCCtrBits = coreParams.SCCtrBits 502 val SCHistLens = coreParams.SCHistLens 503 val SCNTables = coreParams.SCNTables 504 505 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 506 case ((n, cb), h) => (n, cb, h) 507 } 508 val ITTageTableInfos = coreParams.ITTageTableInfos 509 type FoldedHistoryInfo = Tuple2[Int, Int] 510 val foldedGHistInfos = 511 (TageTableInfos.map{ case (nRows, h, t) => 512 if (h > 0) 513 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 514 else 515 Set[FoldedHistoryInfo]() 516 }.reduce(_++_).toSet ++ 517 SCTableInfos.map{ case (nRows, _, h) => 518 if (h > 0) 519 Set((h, min(log2Ceil(nRows/TageBanks), h))) 520 else 521 Set[FoldedHistoryInfo]() 522 }.reduce(_++_).toSet ++ 523 ITTageTableInfos.map{ case (nRows, h, t) => 524 if (h > 0) 525 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 526 else 527 Set[FoldedHistoryInfo]() 528 }.reduce(_++_) ++ 529 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 530 ).toList 531 532 533 534 val CacheLineSize = coreParams.CacheLineSize 535 val CacheLineHalfWord = CacheLineSize / 16 536 val ExtHistoryLength = HistoryLength + 64 537 val IBufSize = coreParams.IBufSize 538 val DecodeWidth = coreParams.DecodeWidth 539 val RenameWidth = coreParams.RenameWidth 540 val CommitWidth = coreParams.CommitWidth 541 val MaxUopSize = coreParams.MaxUopSize 542 val FtqSize = coreParams.FtqSize 543 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 544 val IntLogicRegs = coreParams.IntLogicRegs 545 val FpLogicRegs = coreParams.FpLogicRegs 546 val VecLogicRegs = coreParams.VecLogicRegs 547 val VCONFIG_IDX = coreParams.VCONFIG_IDX 548 val IntPhyRegs = coreParams.intPreg.numEntries 549 val VfPhyRegs = coreParams.vfPreg.numEntries 550 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 551 val RobSize = coreParams.RobSize 552 val RabSize = coreParams.RabSize 553 val IntRefCounterWidth = log2Ceil(RobSize) 554 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 555 val LoadQueueRARSize = coreParams.LoadQueueRARSize 556 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 557 val RollbackGroupSize = coreParams.RollbackGroupSize 558 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 559 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 560 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 561 val StoreQueueSize = coreParams.StoreQueueSize 562 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 563 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 564 val VlsQueueSize = coreParams.VlsQueueSize 565 val dpParams = coreParams.dpParams 566 567 def backendParams: BackendParams = coreParams.backendParams 568 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 569 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 570 val LoadPipelineWidth = coreParams.LoadPipelineWidth 571 val StorePipelineWidth = coreParams.StorePipelineWidth 572 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 573 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 574 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 575 val StoreBufferSize = coreParams.StoreBufferSize 576 val StoreBufferThreshold = coreParams.StoreBufferThreshold 577 val EnsbufferWidth = coreParams.EnsbufferWidth 578 val UncacheBufferSize = coreParams.UncacheBufferSize 579 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 580 val EnableFastForward = coreParams.EnableFastForward 581 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 582 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 583 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 584 val EnableDCacheWPU = coreParams.EnableDCacheWPU 585 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 586 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 587 val asidLen = coreParams.MMUAsidLen 588 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 589 val refillBothTlb = coreParams.refillBothTlb 590 val itlbParams = coreParams.itlbParameters 591 val ldtlbParams = coreParams.ldtlbParameters 592 val sttlbParams = coreParams.sttlbParameters 593 val pftlbParams = coreParams.pftlbParameters 594 val btlbParams = coreParams.btlbParameters 595 val l2tlbParams = coreParams.l2tlbParameters 596 val NumPerfCounters = coreParams.NumPerfCounters 597 598 val instBytes = if (HasCExtension) 2 else 4 599 val instOffsetBits = log2Ceil(instBytes) 600 601 val icacheParameters = coreParams.icacheParameters 602 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 603 604 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 605 // for constrained LR/SC loop 606 val LRSCCycles = 64 607 // for lr storm 608 val LRSCBackOff = 8 609 610 // cache hierarchy configurations 611 val l1BusDataWidth = 256 612 613 // load violation predict 614 val ResetTimeMax2Pow = 20 //1078576 615 val ResetTimeMin2Pow = 10 //1024 616 // wait table parameters 617 val WaitTableSize = 1024 618 val MemPredPCWidth = log2Up(WaitTableSize) 619 val LWTUse2BitCounter = true 620 // store set parameters 621 val SSITSize = WaitTableSize 622 val LFSTSize = 32 623 val SSIDWidth = log2Up(LFSTSize) 624 val LFSTWidth = 4 625 val StoreSetEnable = true // LWT will be disabled if SS is enabled 626 val LFSTEnable = false 627 628 val PCntIncrStep: Int = 6 629 val numPCntHc: Int = 25 630 val numPCntPtw: Int = 19 631 632 val numCSRPCntFrontend = 8 633 val numCSRPCntCtrl = 8 634 val numCSRPCntLsu = 8 635 val numCSRPCntHc = 5 636 637 // source stages of cancel signal to issue queues 638 val cancelStages = Seq("IS", "OG0", "OG1") 639} 640