1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.frontend.icache.ICacheParameters 29import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 30import freechips.rocketchip.diplomacy.AddressSet 31import system.SoCParamsKey 32import scala.math.min 33 34case object XSTileKey extends Field[Seq[XSCoreParameters]] 35 36case object XSCoreParamsKey extends Field[XSCoreParameters] 37 38case class XSCoreParameters 39( 40 HasPrefetch: Boolean = false, 41 HartId: Int = 0, 42 XLEN: Int = 64, 43 HasMExtension: Boolean = true, 44 HasCExtension: Boolean = true, 45 HasDiv: Boolean = true, 46 HasICache: Boolean = true, 47 HasDCache: Boolean = true, 48 AddrBits: Int = 64, 49 VAddrBits: Int = 39, 50 HasFPU: Boolean = true, 51 HasCustomCSRCacheOp: Boolean = true, 52 FetchWidth: Int = 8, 53 AsidLength: Int = 16, 54 EnableBPU: Boolean = true, 55 EnableBPD: Boolean = true, 56 EnableRAS: Boolean = true, 57 EnableLB: Boolean = false, 58 EnableLoop: Boolean = true, 59 EnableSC: Boolean = true, 60 EnbaleTlbDebug: Boolean = false, 61 EnableJal: Boolean = false, 62 EnableUBTB: Boolean = true, 63 HistoryLength: Int = 256, 64 PathHistoryLength: Int = 16, 65 BtbSize: Int = 2048, 66 JbtacSize: Int = 1024, 67 JbtacBanks: Int = 8, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 UBtbWays: Int = 16, 71 BtbWays: Int = 2, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 Seq(( 128*8, 2, 7), 75 ( 128*8, 4, 7), 76 ( 256*8, 8, 8), 77 ( 256*8, 16, 8), 78 ( 128*8, 32, 9), 79 ( 128*8, 65, 9)), 80 TageBanks: Int = 2, 81 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 82 // Sets Hist Tag 83 Seq(( 512, 0, 0), 84 ( 256, 4, 8), 85 ( 256, 8, 8), 86 ( 512, 12, 8), 87 ( 512, 16, 8), 88 ( 512, 32, 8)), 89 SCNRows: Int = 1024, 90 SCNTables: Int = 6, 91 SCCtrBits: Int = 6, 92 numBr: Int = 2, 93 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 94 ((resp_in: BranchPredictionResp, p: Parameters) => { 95 // val loop = Module(new LoopPredictor) 96 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 97 // else Module(new Tage) } 98 // else { Module(new FakeTage) }) 99 val ftb = Module(new FTB()(p)) 100 val ubtb = Module(new MicroBTB()(p)) 101 val bim = Module(new BIM()(p)) 102 val tage = Module(new Tage_SC()(p)) 103 val ras = Module(new RAS()(p)) 104 val ittage = Module(new ITTage()(p)) 105 // val tage = Module(new Tage()(p)) 106 // val fake = Module(new FakePredictor()(p)) 107 108 // val preds = Seq(loop, tage, btb, ubtb, bim) 109 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 110 preds.map(_.io := DontCare) 111 112 // ubtb.io.resp_in(0) := resp_in 113 // bim.io.resp_in(0) := ubtb.io.resp 114 // btb.io.resp_in(0) := bim.io.resp 115 // tage.io.resp_in(0) := btb.io.resp 116 // loop.io.resp_in(0) := tage.io.resp 117 bim.io.in.bits.resp_in(0) := resp_in 118 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 119 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 120 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 121 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 122 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 123 124 (preds, ras.io.out.resp) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 FtqSize: Int = 64, 131 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 132 IssQueSize: Int = 16, 133 NRPhyRegs: Int = 192, 134 LoadQueueSize: Int = 80, 135 StoreQueueSize: Int = 64, 136 RobSize: Int = 256, 137 dpParams: DispatchParameters = DispatchParameters( 138 IntDqSize = 16, 139 FpDqSize = 16, 140 LsDqSize = 16, 141 IntDqDeqWidth = 4, 142 FpDqDeqWidth = 4, 143 LsDqDeqWidth = 4 144 ), 145 exuParameters: ExuParameters = ExuParameters( 146 JmpCnt = 1, 147 AluCnt = 4, 148 MulCnt = 0, 149 MduCnt = 2, 150 FmacCnt = 4, 151 FmiscCnt = 2, 152 FmiscDivSqrtCnt = 0, 153 LduCnt = 2, 154 StuCnt = 2 155 ), 156 LoadPipelineWidth: Int = 2, 157 StorePipelineWidth: Int = 2, 158 StoreBufferSize: Int = 16, 159 StoreBufferThreshold: Int = 7, 160 EnableLoadToLoadForward: Boolean = false, 161 EnableFastForward: Boolean = false, 162 EnableLdVioCheckAfterReset: Boolean = true, 163 RefillSize: Int = 512, 164 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 165 itlbParameters: TLBParameters = TLBParameters( 166 name = "itlb", 167 fetchi = true, 168 useDmode = false, 169 sameCycle = true, 170 normalNWays = 32, 171 normalReplacer = Some("plru"), 172 superNWays = 4, 173 superReplacer = Some("plru"), 174 shouldBlock = true 175 ), 176 ldtlbParameters: TLBParameters = TLBParameters( 177 name = "ldtlb", 178 normalNSets = 128, 179 normalNWays = 1, 180 normalAssociative = "sa", 181 normalReplacer = Some("setplru"), 182 superNWays = 8, 183 normalAsVictim = true, 184 outReplace = true, 185 saveLevel = true 186 ), 187 sttlbParameters: TLBParameters = TLBParameters( 188 name = "sttlb", 189 normalNSets = 128, 190 normalNWays = 1, 191 normalAssociative = "sa", 192 normalReplacer = Some("setplru"), 193 superNWays = 8, 194 normalAsVictim = true, 195 outReplace = true, 196 saveLevel = true 197 ), 198 refillBothTlb: Boolean = false, 199 btlbParameters: TLBParameters = TLBParameters( 200 name = "btlb", 201 normalNSets = 1, 202 normalNWays = 64, 203 superNWays = 4, 204 ), 205 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 206 NumPMP: Int = 16, // 0 or 16 or 64 207 NumPMA: Int = 16, 208 NumPerfCounters: Int = 16, 209 icacheParameters: ICacheParameters = ICacheParameters( 210 tagECC = Some("parity"), 211 dataECC = Some("parity"), 212 replacer = Some("setplru"), 213 nMissEntries = 2, 214 nReleaseEntries = 2 215 ), 216 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 217 tagECC = Some("secded"), 218 dataECC = Some("secded"), 219 replacer = Some("setplru"), 220 nMissEntries = 16, 221 nProbeEntries = 8, 222 nReleaseEntries = 18 223 )), 224 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 225 name = "l2", 226 level = 2, 227 ways = 8, 228 sets = 1024, // default 512KB L2 229 prefetch = Some(huancun.prefetch.BOPParameters()) 230 )), 231 L2NBanks: Int = 1, 232 usePTWRepeater: Boolean = false, 233 softPTW: Boolean = false // dpi-c debug only 234){ 235 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 236 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 237 238 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 239 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 240 241 val fpExuConfigs = 242 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 243 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 244 245 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 246} 247 248case object DebugOptionsKey extends Field[DebugOptions] 249 250case class DebugOptions 251( 252 FPGAPlatform: Boolean = false, 253 EnableDifftest: Boolean = false, 254 AlwaysBasicDiff: Boolean = true, 255 EnableDebug: Boolean = false, 256 EnablePerfDebug: Boolean = true, 257 UseDRAMSim: Boolean = false 258) 259 260trait HasXSParameter { 261 262 implicit val p: Parameters 263 264 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 265 266 val coreParams = p(XSCoreParamsKey) 267 val env = p(DebugOptionsKey) 268 269 val XLEN = coreParams.XLEN 270 val minFLen = 32 271 val fLen = 64 272 def xLen = XLEN 273 274 val HasMExtension = coreParams.HasMExtension 275 val HasCExtension = coreParams.HasCExtension 276 val HasDiv = coreParams.HasDiv 277 val HasIcache = coreParams.HasICache 278 val HasDcache = coreParams.HasDCache 279 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 280 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 281 val AsidLength = coreParams.AsidLength 282 val AddrBytes = AddrBits / 8 // unused 283 val DataBits = XLEN 284 val DataBytes = DataBits / 8 285 val HasFPU = coreParams.HasFPU 286 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 287 val FetchWidth = coreParams.FetchWidth 288 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 289 val EnableBPU = coreParams.EnableBPU 290 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 291 val EnableRAS = coreParams.EnableRAS 292 val EnableLB = coreParams.EnableLB 293 val EnableLoop = coreParams.EnableLoop 294 val EnableSC = coreParams.EnableSC 295 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 296 val HistoryLength = coreParams.HistoryLength 297 val PathHistoryLength = coreParams.PathHistoryLength 298 val BtbSize = coreParams.BtbSize 299 // val BtbWays = 4 300 val BtbBanks = PredictWidth 301 // val BtbSets = BtbSize / BtbWays 302 val JbtacSize = coreParams.JbtacSize 303 val JbtacBanks = coreParams.JbtacBanks 304 val RasSize = coreParams.RasSize 305 306 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 307 coreParams.branchPredictor(resp_in, p) 308 } 309 val numBr = coreParams.numBr 310 val TageTableInfos = coreParams.TageTableInfos 311 312 313 val BankTageTableInfos = (0 until numBr).map(i => 314 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 315 ) 316 val TageBanks = coreParams.TageBanks 317 val SCNRows = coreParams.SCNRows 318 val SCCtrBits = coreParams.SCCtrBits 319 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 320 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 321 322 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 323 case (ntable, histlens) => 324 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 325 } 326 val ITTageTableInfos = coreParams.ITTageTableInfos 327 type FoldedHistoryInfo = Tuple2[Int, Int] 328 val foldedGHistInfos = 329 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 330 if (h > 0) 331 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 332 else 333 Set[FoldedHistoryInfo]() 334 }.reduce(_++_)).toSet ++ 335 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 336 if (h > 0) 337 Set((h, min(log2Ceil(nRows/TageBanks), h))) 338 else 339 Set[FoldedHistoryInfo]() 340 }.reduce(_++_)).toSet ++ 341 ITTageTableInfos.map{ case (nRows, h, t) => 342 if (h > 0) 343 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 344 else 345 Set[FoldedHistoryInfo]() 346 }.reduce(_++_)).toList 347 348 val CacheLineSize = coreParams.CacheLineSize 349 val CacheLineHalfWord = CacheLineSize / 16 350 val ExtHistoryLength = HistoryLength + 64 351 val UBtbWays = coreParams.UBtbWays 352 val BtbWays = coreParams.BtbWays 353 val IBufSize = coreParams.IBufSize 354 val DecodeWidth = coreParams.DecodeWidth 355 val RenameWidth = coreParams.RenameWidth 356 val CommitWidth = coreParams.CommitWidth 357 val FtqSize = coreParams.FtqSize 358 val IssQueSize = coreParams.IssQueSize 359 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 360 val NRPhyRegs = coreParams.NRPhyRegs 361 val PhyRegIdxWidth = log2Up(NRPhyRegs) 362 val RobSize = coreParams.RobSize 363 val IntRefCounterWidth = log2Ceil(RobSize) 364 val LoadQueueSize = coreParams.LoadQueueSize 365 val StoreQueueSize = coreParams.StoreQueueSize 366 val dpParams = coreParams.dpParams 367 val exuParameters = coreParams.exuParameters 368 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 369 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 370 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 371 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 372 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 373 val LoadPipelineWidth = coreParams.LoadPipelineWidth 374 val StorePipelineWidth = coreParams.StorePipelineWidth 375 val StoreBufferSize = coreParams.StoreBufferSize 376 val StoreBufferThreshold = coreParams.StoreBufferThreshold 377 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 378 val EnableFastForward = coreParams.EnableFastForward 379 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 380 val RefillSize = coreParams.RefillSize 381 val asidLen = coreParams.MMUAsidLen 382 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 383 val refillBothTlb = coreParams.refillBothTlb 384 val itlbParams = coreParams.itlbParameters 385 val ldtlbParams = coreParams.ldtlbParameters 386 val sttlbParams = coreParams.sttlbParameters 387 val btlbParams = coreParams.btlbParameters 388 val l2tlbParams = coreParams.l2tlbParameters 389 val NumPMP = coreParams.NumPMP 390 val NumPMA = coreParams.NumPMA 391 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 392 val NumPerfCounters = coreParams.NumPerfCounters 393 394 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 395 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 396 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 397 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 398 399 val instBytes = if (HasCExtension) 2 else 4 400 val instOffsetBits = log2Ceil(instBytes) 401 402 val icacheParameters = coreParams.icacheParameters 403 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 404 405 val LRSCCycles = 100 406 407 // cache hierarchy configurations 408 val l1BusDataWidth = 256 409 410 // load violation predict 411 val ResetTimeMax2Pow = 20 //1078576 412 val ResetTimeMin2Pow = 10 //1024 413 // wait table parameters 414 val WaitTableSize = 1024 415 val MemPredPCWidth = log2Up(WaitTableSize) 416 val LWTUse2BitCounter = true 417 // store set parameters 418 val SSITSize = WaitTableSize 419 val LFSTSize = 32 420 val SSIDWidth = log2Up(LFSTSize) 421 val LFSTWidth = 4 422 val StoreSetEnable = true // LWT will be disabled if SS is enabled 423 424 val loadExuConfigs = coreParams.loadExuConfigs 425 val storeExuConfigs = coreParams.storeExuConfigs 426 427 val intExuConfigs = coreParams.intExuConfigs 428 429 val fpExuConfigs = coreParams.fpExuConfigs 430 431 val exuConfigs = coreParams.exuConfigs 432 433 val PCntIncrStep: Int = 6 434 val numPCntHc: Int = 25 435 val numPCntPtw: Int = 19 436 437 val numCSRPCntFrontend = 8 438 val numCSRPCntCtrl = 8 439 val numCSRPCntLsu = 8 440 val numCSRPCntHc = 5 441 val print_perfcounter = false 442} 443