1package xiangshan 2 3import chipsalliance.rocketchip.config.{Field, Parameters} 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.exu._ 7import xiangshan.backend.fu._ 8import xiangshan.backend.fu.fpu._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 11import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 12 13case object XSCoreParamsKey extends Field[XSCoreParameters] 14 15case class XSCoreParameters 16( 17 HasL2Cache: Boolean = false, 18 HasPrefetch: Boolean = false, 19 HartId: Int = 0, 20 XLEN: Int = 64, 21 HasMExtension: Boolean = true, 22 HasCExtension: Boolean = true, 23 HasDiv: Boolean = true, 24 HasICache: Boolean = true, 25 HasDCache: Boolean = true, 26 EnableStoreQueue: Boolean = true, 27 AddrBits: Int = 64, 28 VAddrBits: Int = 39, 29 PAddrBits: Int = 40, 30 HasFPU: Boolean = true, 31 FetchWidth: Int = 8, 32 EnableBPU: Boolean = true, 33 EnableBPD: Boolean = true, 34 EnableRAS: Boolean = true, 35 EnableLB: Boolean = false, 36 EnableLoop: Boolean = true, 37 EnableSC: Boolean = true, 38 EnbaleTlbDebug: Boolean = false, 39 EnableJal: Boolean = false, 40 EnableUBTB: Boolean = true, 41 HistoryLength: Int = 64, 42 BtbSize: Int = 2048, 43 JbtacSize: Int = 1024, 44 JbtacBanks: Int = 8, 45 RasSize: Int = 16, 46 CacheLineSize: Int = 512, 47 UBtbWays: Int = 16, 48 BtbWays: Int = 2, 49 50 EnableL1plusPrefetcher: Boolean = true, 51 IBufSize: Int = 48, 52 DecodeWidth: Int = 6, 53 RenameWidth: Int = 6, 54 CommitWidth: Int = 6, 55 BrqSize: Int = 32, 56 FtqSize: Int = 48, 57 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 58 IssQueSize: Int = 16, 59 NRPhyRegs: Int = 160, 60 NRIntReadPorts: Int = 14, 61 NRIntWritePorts: Int = 8, 62 NRFpReadPorts: Int = 14, 63 NRFpWritePorts: Int = 8, 64 LoadQueueSize: Int = 64, 65 StoreQueueSize: Int = 48, 66 RoqSize: Int = 192, 67 dpParams: DispatchParameters = DispatchParameters( 68 IntDqSize = 16, 69 FpDqSize = 16, 70 LsDqSize = 16, 71 IntDqDeqWidth = 4, 72 FpDqDeqWidth = 4, 73 LsDqDeqWidth = 4 74 ), 75 exuParameters: ExuParameters = ExuParameters( 76 JmpCnt = 1, 77 AluCnt = 4, 78 MulCnt = 0, 79 MduCnt = 2, 80 FmacCnt = 4, 81 FmiscCnt = 2, 82 FmiscDivSqrtCnt = 0, 83 LduCnt = 2, 84 StuCnt = 2 85 ), 86 LoadPipelineWidth: Int = 2, 87 StorePipelineWidth: Int = 2, 88 StoreBufferSize: Int = 16, 89 RefillSize: Int = 512, 90 TlbEntrySize: Int = 32, 91 TlbSPEntrySize: Int = 4, 92 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 93 PtwSPEntrySize: Int = 16, 94 PtwL1EntrySize: Int = 16, 95 PtwL2EntrySize: Int = 2048, //(256 * 8) 96 NumPerfCounters: Int = 16, 97){ 98 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 99 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 100 101 val intExuConfigs = JumpExeUnitCfg +: ( 102 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++ 103 Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) 104 ) 105 106 val fpExuConfigs = 107 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 108 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 109 110 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 111} 112 113case object DebugOptionsKey extends Field[DebugOptions] 114 115case class DebugOptions 116( 117 FPGAPlatform: Boolean = true, 118 EnableDebug: Boolean = true, 119 EnablePerfDebug: Boolean = true, 120 UseDRAMSim: Boolean = false 121) 122 123trait HasXSParameter { 124 125 implicit val p: Parameters 126 127 val coreParams = p(XSCoreParamsKey) 128 val env = p(DebugOptionsKey) 129 130 val XLEN = coreParams.XLEN 131 val hardId = coreParams.HartId 132 val minFLen = 32 133 val fLen = 64 134 def xLen = XLEN 135 136 val HasMExtension = coreParams.HasMExtension 137 val HasCExtension = coreParams.HasCExtension 138 val HasDiv = coreParams.HasDiv 139 val HasIcache = coreParams.HasICache 140 val HasDcache = coreParams.HasDCache 141 val EnableStoreQueue = coreParams.EnableStoreQueue 142 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 143 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 144 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 145 val AddrBytes = AddrBits / 8 // unused 146 val DataBits = XLEN 147 val DataBytes = DataBits / 8 148 val HasFPU = coreParams.HasFPU 149 val FetchWidth = coreParams.FetchWidth 150 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 151 val EnableBPU = coreParams.EnableBPU 152 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 153 val EnableRAS = coreParams.EnableRAS 154 val EnableLB = coreParams.EnableLB 155 val EnableLoop = coreParams.EnableLoop 156 val EnableSC = coreParams.EnableSC 157 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 158 val HistoryLength = coreParams.HistoryLength 159 val BtbSize = coreParams.BtbSize 160 // val BtbWays = 4 161 val BtbBanks = PredictWidth 162 // val BtbSets = BtbSize / BtbWays 163 val JbtacSize = coreParams.JbtacSize 164 val JbtacBanks = coreParams.JbtacBanks 165 val RasSize = coreParams.RasSize 166 val CacheLineSize = coreParams.CacheLineSize 167 val CacheLineHalfWord = CacheLineSize / 16 168 val ExtHistoryLength = HistoryLength + 64 169 val UBtbWays = coreParams.UBtbWays 170 val BtbWays = coreParams.BtbWays 171 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 172 val IBufSize = coreParams.IBufSize 173 val DecodeWidth = coreParams.DecodeWidth 174 val RenameWidth = coreParams.RenameWidth 175 val CommitWidth = coreParams.CommitWidth 176 val BrqSize = coreParams.BrqSize 177 val FtqSize = coreParams.FtqSize 178 val IssQueSize = coreParams.IssQueSize 179 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 180 val BrTagWidth = log2Up(BrqSize) 181 val NRPhyRegs = coreParams.NRPhyRegs 182 val PhyRegIdxWidth = log2Up(NRPhyRegs) 183 val RoqSize = coreParams.RoqSize 184 val LoadQueueSize = coreParams.LoadQueueSize 185 val StoreQueueSize = coreParams.StoreQueueSize 186 val dpParams = coreParams.dpParams 187 val exuParameters = coreParams.exuParameters 188 val NRIntReadPorts = coreParams.NRIntReadPorts 189 val NRIntWritePorts = coreParams.NRIntWritePorts 190 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 191 val NRFpReadPorts = coreParams.NRFpReadPorts 192 val NRFpWritePorts = coreParams.NRFpWritePorts 193 val LoadPipelineWidth = coreParams.LoadPipelineWidth 194 val StorePipelineWidth = coreParams.StorePipelineWidth 195 val StoreBufferSize = coreParams.StoreBufferSize 196 val RefillSize = coreParams.RefillSize 197 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 198 val TlbEntrySize = coreParams.TlbEntrySize 199 val TlbSPEntrySize = coreParams.TlbSPEntrySize 200 val useFakePTW = false 201 val PtwL3EntrySize = coreParams.PtwL3EntrySize 202 val PtwSPEntrySize = coreParams.PtwSPEntrySize 203 val PtwL1EntrySize = coreParams.PtwL1EntrySize 204 val PtwL2EntrySize = coreParams.PtwL2EntrySize 205 val NumPerfCounters = coreParams.NumPerfCounters 206 207 val instBytes = if (HasCExtension) 2 else 4 208 val instOffsetBits = log2Ceil(instBytes) 209 210 val icacheParameters = ICacheParameters( 211 tagECC = Some("parity"), 212 dataECC = Some("parity"), 213 replacer = Some("setplru"), 214 nMissEntries = 2 215 ) 216 217 val useFakeL1plusCache = false 218 val l1plusCacheParameters = L1plusCacheParameters( 219 tagECC = Some("secded"), 220 dataECC = Some("secded"), 221 replacer = Some("setplru"), 222 nMissEntries = 8 223 ) 224 225 val useFakeDCache = false 226 val dcacheParameters = DCacheParameters( 227 tagECC = Some("secded"), 228 dataECC = Some("secded"), 229 replacer = Some("setplru"), 230 nMissEntries = 16, 231 nProbeEntries = 16, 232 nReleaseEntries = 16, 233 nStoreReplayEntries = 16 234 ) 235 236 val LRSCCycles = 100 237 238 239 // cache hierarchy configurations 240 val l1BusDataWidth = 256 241 242 // L2 configurations 243 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache 244 val L1BusWidth = 256 245 val L2Size = 512 * 1024 // 512KB 246 val L2BlockSize = 64 247 val L2NWays = 8 248 val L2NSets = L2Size / L2BlockSize / L2NWays 249 250 // L3 configurations 251 val L2BusWidth = 256 252 253 // icache prefetcher 254 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 255 enable = true, 256 _type = "stream", 257 streamParams = StreamPrefetchParameters( 258 streamCnt = 2, 259 streamSize = 4, 260 ageWidth = 4, 261 blockBytes = l1plusCacheParameters.blockBytes, 262 reallocStreamOnMissInstantly = true, 263 cacheName = "icache" 264 ) 265 ) 266 267 // dcache prefetcher 268 val l2PrefetcherParameters = L2PrefetcherParameters( 269 enable = true, 270 _type = "bop", // "stream" or "bop" 271 streamParams = StreamPrefetchParameters( 272 streamCnt = 4, 273 streamSize = 4, 274 ageWidth = 4, 275 blockBytes = L2BlockSize, 276 reallocStreamOnMissInstantly = true, 277 cacheName = "dcache" 278 ), 279 bopParams = BOPParameters( 280 rrTableEntries = 256, 281 rrTagBits = 12, 282 scoreBits = 5, 283 roundMax = 50, 284 badScore = 1, 285 blockBytes = L2BlockSize, 286 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 287 ), 288 ) 289 290 val loadExuConfigs = coreParams.loadExuConfigs 291 val storeExuConfigs = coreParams.storeExuConfigs 292 293 val intExuConfigs = coreParams.intExuConfigs 294 295 val fpExuConfigs = coreParams.fpExuConfigs 296 297 val exuConfigs = coreParams.exuConfigs 298 299} 300