1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31 32case object XSTileKey extends Field[Seq[XSCoreParameters]] 33 34case object XSCoreParamsKey extends Field[XSCoreParameters] 35 36case class XSCoreParameters 37( 38 HasPrefetch: Boolean = false, 39 HartId: Int = 0, 40 XLEN: Int = 64, 41 HasMExtension: Boolean = true, 42 HasCExtension: Boolean = true, 43 HasDiv: Boolean = true, 44 HasICache: Boolean = true, 45 HasDCache: Boolean = true, 46 AddrBits: Int = 64, 47 VAddrBits: Int = 39, 48 HasFPU: Boolean = true, 49 HasCustomCSRCacheOp: Boolean = true, 50 FetchWidth: Int = 8, 51 AsidLength: Int = 16, 52 EnableBPU: Boolean = true, 53 EnableBPD: Boolean = true, 54 EnableRAS: Boolean = true, 55 EnableLB: Boolean = false, 56 EnableLoop: Boolean = true, 57 EnableSC: Boolean = true, 58 EnbaleTlbDebug: Boolean = false, 59 EnableJal: Boolean = false, 60 EnableUBTB: Boolean = true, 61 HistoryLength: Int = 64, 62 PathHistoryLength: Int = 16, 63 BtbSize: Int = 2048, 64 JbtacSize: Int = 1024, 65 JbtacBanks: Int = 8, 66 RasSize: Int = 32, 67 CacheLineSize: Int = 512, 68 UBtbWays: Int = 16, 69 BtbWays: Int = 2, 70 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 71 ((resp_in: BranchPredictionResp, p: Parameters) => { 72 // val loop = Module(new LoopPredictor) 73 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 74 // else Module(new Tage) } 75 // else { Module(new FakeTage) }) 76 val ftb = Module(new FTB()(p)) 77 val ubtb = Module(new MicroBTB()(p)) 78 val bim = Module(new BIM()(p)) 79 val tage = Module(new Tage_SC()(p)) 80 val ras = Module(new RAS()(p)) 81 val ittage = Module(new ITTage()(p)) 82 // val tage = Module(new Tage()(p)) 83 // val fake = Module(new FakePredictor()(p)) 84 85 // val preds = Seq(loop, tage, btb, ubtb, bim) 86 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 87 preds.map(_.io := DontCare) 88 89 // ubtb.io.resp_in(0) := resp_in 90 // bim.io.resp_in(0) := ubtb.io.resp 91 // btb.io.resp_in(0) := bim.io.resp 92 // tage.io.resp_in(0) := btb.io.resp 93 // loop.io.resp_in(0) := tage.io.resp 94 bim.io.in.bits.resp_in(0) := resp_in 95 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 96 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 97 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 98 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 99 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 100 101 (preds, ras.io.out.resp) 102 }), 103 IBufSize: Int = 48, 104 DecodeWidth: Int = 6, 105 RenameWidth: Int = 6, 106 CommitWidth: Int = 6, 107 FtqSize: Int = 64, 108 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 109 IssQueSize: Int = 16, 110 NRPhyRegs: Int = 192, 111 NRIntReadPorts: Int = 14, 112 NRIntWritePorts: Int = 8, 113 NRFpReadPorts: Int = 14, 114 NRFpWritePorts: Int = 8, 115 LoadQueueSize: Int = 80, 116 StoreQueueSize: Int = 64, 117 RobSize: Int = 256, 118 dpParams: DispatchParameters = DispatchParameters( 119 IntDqSize = 16, 120 FpDqSize = 16, 121 LsDqSize = 16, 122 IntDqDeqWidth = 4, 123 FpDqDeqWidth = 4, 124 LsDqDeqWidth = 4 125 ), 126 exuParameters: ExuParameters = ExuParameters( 127 JmpCnt = 1, 128 AluCnt = 4, 129 MulCnt = 0, 130 MduCnt = 2, 131 FmacCnt = 4, 132 FmiscCnt = 2, 133 FmiscDivSqrtCnt = 0, 134 LduCnt = 2, 135 StuCnt = 2 136 ), 137 LoadPipelineWidth: Int = 2, 138 StorePipelineWidth: Int = 2, 139 StoreBufferSize: Int = 16, 140 StoreBufferThreshold: Int = 7, 141 EnableFastForward: Boolean = true, 142 EnableLdVioCheckAfterReset: Boolean = true, 143 RefillSize: Int = 512, 144 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 145 itlbParameters: TLBParameters = TLBParameters( 146 name = "itlb", 147 fetchi = true, 148 useDmode = false, 149 sameCycle = true, 150 normalNWays = 32, 151 normalReplacer = Some("plru"), 152 superNWays = 4, 153 superReplacer = Some("plru"), 154 shouldBlock = true 155 ), 156 ldtlbParameters: TLBParameters = TLBParameters( 157 name = "ldtlb", 158 normalNSets = 128, 159 normalNWays = 1, 160 normalAssociative = "sa", 161 normalReplacer = Some("setplru"), 162 superNWays = 8, 163 normalAsVictim = true, 164 outReplace = true 165 ), 166 sttlbParameters: TLBParameters = TLBParameters( 167 name = "sttlb", 168 normalNSets = 128, 169 normalNWays = 1, 170 normalAssociative = "sa", 171 normalReplacer = Some("setplru"), 172 superNWays = 8, 173 normalAsVictim = true, 174 outReplace = true 175 ), 176 refillBothTlb: Boolean = false, 177 btlbParameters: TLBParameters = TLBParameters( 178 name = "btlb", 179 normalNSets = 1, 180 normalNWays = 64, 181 superNWays = 4, 182 ), 183 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 184 NumPMP: Int = 16, // 0 or 16 or 64 185 NumPMA: Int = 16, 186 NumPerfCounters: Int = 16, 187 icacheParameters: ICacheParameters = ICacheParameters( 188 tagECC = Some("parity"), 189 dataECC = Some("parity"), 190 replacer = Some("setplru"), 191 nMissEntries = 2 192 ), 193 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 194 tagECC = Some("secded"), 195 dataECC = Some("secded"), 196 replacer = Some("setplru"), 197 nMissEntries = 16, 198 nProbeEntries = 8, 199 nReleaseEntries = 18 200 )), 201 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 202 name = "l2", 203 level = 2, 204 ways = 8, 205 sets = 1024, // default 512KB L2 206 prefetch = Some(huancun.prefetch.BOPParameters()) 207 )), 208 L2NBanks: Int = 1, 209 usePTWRepeater: Boolean = false, 210 softPTW: Boolean = false // dpi-c debug only 211){ 212 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 213 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 214 215 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 216 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 217 218 val fpExuConfigs = 219 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 220 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 221 222 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 223} 224 225case object DebugOptionsKey extends Field[DebugOptions] 226 227case class DebugOptions 228( 229 FPGAPlatform: Boolean = false, 230 EnableDifftest: Boolean = false, 231 EnableDebug: Boolean = false, 232 EnablePerfDebug: Boolean = true, 233 UseDRAMSim: Boolean = false 234) 235 236trait HasXSParameter { 237 238 implicit val p: Parameters 239 240 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 241 242 val coreParams = p(XSCoreParamsKey) 243 val env = p(DebugOptionsKey) 244 245 val XLEN = coreParams.XLEN 246 val hardId = coreParams.HartId 247 val minFLen = 32 248 val fLen = 64 249 def xLen = XLEN 250 251 val HasMExtension = coreParams.HasMExtension 252 val HasCExtension = coreParams.HasCExtension 253 val HasDiv = coreParams.HasDiv 254 val HasIcache = coreParams.HasICache 255 val HasDcache = coreParams.HasDCache 256 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 257 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 258 val AsidLength = coreParams.AsidLength 259 val AddrBytes = AddrBits / 8 // unused 260 val DataBits = XLEN 261 val DataBytes = DataBits / 8 262 val HasFPU = coreParams.HasFPU 263 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 264 val FetchWidth = coreParams.FetchWidth 265 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 266 val EnableBPU = coreParams.EnableBPU 267 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 268 val EnableRAS = coreParams.EnableRAS 269 val EnableLB = coreParams.EnableLB 270 val EnableLoop = coreParams.EnableLoop 271 val EnableSC = coreParams.EnableSC 272 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 273 val HistoryLength = coreParams.HistoryLength 274 val PathHistoryLength = coreParams.PathHistoryLength 275 val BtbSize = coreParams.BtbSize 276 // val BtbWays = 4 277 val BtbBanks = PredictWidth 278 // val BtbSets = BtbSize / BtbWays 279 val JbtacSize = coreParams.JbtacSize 280 val JbtacBanks = coreParams.JbtacBanks 281 val RasSize = coreParams.RasSize 282 283 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 284 coreParams.branchPredictor(resp_in, p) 285 } 286 287 val CacheLineSize = coreParams.CacheLineSize 288 val CacheLineHalfWord = CacheLineSize / 16 289 val ExtHistoryLength = HistoryLength + 64 290 val UBtbWays = coreParams.UBtbWays 291 val BtbWays = coreParams.BtbWays 292 val IBufSize = coreParams.IBufSize 293 val DecodeWidth = coreParams.DecodeWidth 294 val RenameWidth = coreParams.RenameWidth 295 val CommitWidth = coreParams.CommitWidth 296 val FtqSize = coreParams.FtqSize 297 val IssQueSize = coreParams.IssQueSize 298 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 299 val NRPhyRegs = coreParams.NRPhyRegs 300 val PhyRegIdxWidth = log2Up(NRPhyRegs) 301 val RobSize = coreParams.RobSize 302 val IntRefCounterWidth = log2Ceil(RobSize) 303 val StdFreeListSize = NRPhyRegs - 32 304 val MEFreeListSize = NRPhyRegs 305 val LoadQueueSize = coreParams.LoadQueueSize 306 val StoreQueueSize = coreParams.StoreQueueSize 307 val dpParams = coreParams.dpParams 308 val exuParameters = coreParams.exuParameters 309 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 310 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 311 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 312 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 313 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 314 val LoadPipelineWidth = coreParams.LoadPipelineWidth 315 val StorePipelineWidth = coreParams.StorePipelineWidth 316 val StoreBufferSize = coreParams.StoreBufferSize 317 val StoreBufferThreshold = coreParams.StoreBufferThreshold 318 val EnableFastForward = coreParams.EnableFastForward 319 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 320 val RefillSize = coreParams.RefillSize 321 val asidLen = coreParams.MMUAsidLen 322 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 323 val refillBothTlb = coreParams.refillBothTlb 324 val itlbParams = coreParams.itlbParameters 325 val ldtlbParams = coreParams.ldtlbParameters 326 val sttlbParams = coreParams.sttlbParameters 327 val btlbParams = coreParams.btlbParameters 328 val l2tlbParams = coreParams.l2tlbParameters 329 val NumPMP = coreParams.NumPMP 330 val NumPMA = coreParams.NumPMA 331 val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict 332 val NumPerfCounters = coreParams.NumPerfCounters 333 334 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 335 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 336 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 337 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 338 339 val instBytes = if (HasCExtension) 2 else 4 340 val instOffsetBits = log2Ceil(instBytes) 341 342 val icacheParameters = coreParams.icacheParameters 343 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 344 345 val LRSCCycles = 100 346 347 // cache hierarchy configurations 348 val l1BusDataWidth = 256 349 350 // load violation predict 351 val ResetTimeMax2Pow = 20 //1078576 352 val ResetTimeMin2Pow = 10 //1024 353 // wait table parameters 354 val WaitTableSize = 1024 355 val MemPredPCWidth = log2Up(WaitTableSize) 356 val LWTUse2BitCounter = true 357 // store set parameters 358 val SSITSize = WaitTableSize 359 val LFSTSize = 32 360 val SSIDWidth = log2Up(LFSTSize) 361 val LFSTWidth = 4 362 val StoreSetEnable = true // LWT will be disabled if SS is enabled 363 364 val loadExuConfigs = coreParams.loadExuConfigs 365 val storeExuConfigs = coreParams.storeExuConfigs 366 367 val intExuConfigs = coreParams.intExuConfigs 368 369 val fpExuConfigs = coreParams.fpExuConfigs 370 371 val exuConfigs = coreParams.exuConfigs 372 373 val PCntIncrStep: Int = 6 374 val numPCntHc: Int = 25 375 val numPCntPtw: Int = 19 376 377 val numCSRPCntFrontend = 8 378 val numCSRPCntCtrl = 8 379 val numCSRPCntLsu = 8 380 val numCSRPCntHc = 5 381 val print_perfcounter = false 382} 383