1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBitsSv39: Int = 39, 72 GPAddrBitsSv39x4: Int = 41, 73 VAddrBitsSv48: Int = 48, 74 GPAddrBitsSv48x4: Int = 50, 75 HasFPU: Boolean = true, 76 HasVPU: Boolean = true, 77 HasCustomCSRCacheOp: Boolean = true, 78 FetchWidth: Int = 8, 79 AsidLength: Int = 16, 80 VmidLength: Int = 14, 81 EnableBPU: Boolean = true, 82 EnableBPD: Boolean = true, 83 EnableRAS: Boolean = true, 84 EnableLB: Boolean = false, 85 EnableLoop: Boolean = true, 86 EnableSC: Boolean = true, 87 EnbaleTlbDebug: Boolean = false, 88 EnableClockGate: Boolean = true, 89 EnableJal: Boolean = false, 90 EnableFauFTB: Boolean = true, 91 EnableSv48: Boolean = true, 92 UbtbGHRLength: Int = 4, 93 // HistoryLength: Int = 512, 94 EnableGHistDiff: Boolean = true, 95 EnableCommitGHistDiff: Boolean = true, 96 UbtbSize: Int = 256, 97 FtbSize: Int = 2048, 98 RasSize: Int = 16, 99 RasSpecSize: Int = 32, 100 RasCtrSize: Int = 3, 101 CacheLineSize: Int = 512, 102 FtbWays: Int = 4, 103 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 104 // Sets Hist Tag 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 122 (resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val uftb = Module(new FauFTB()(p)) 125 val tage = Module(new Tage_SC()(p)) 126 val ras = Module(new RAS()(p)) 127 val ittage = Module(new ITTage()(p)) 128 val preds = Seq(uftb, tage, ftb, ittage, ras) 129 preds.map(_.io := DontCare) 130 131 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 132 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 133 134 uftb.io.in.bits.resp_in(0) := resp_in 135 tage.io.in.bits.resp_in(0) := uftb.io.out 136 ftb.io.in.bits.resp_in(0) := tage.io.out 137 ittage.io.in.bits.resp_in(0) := ftb.io.out 138 ras.io.in.bits.resp_in(0) := ittage.io.out 139 140 (preds, ras.io.out) 141 }, 142 ICacheForceMetaECCError: Boolean = false, 143 ICacheForceDataECCError: Boolean = false, 144 IBufSize: Int = 48, 145 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 146 DecodeWidth: Int = 6, 147 RenameWidth: Int = 6, 148 CommitWidth: Int = 8, 149 RobCommitWidth: Int = 8, 150 RabCommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 15, // 15: tmp 159 V0LogicRegs: Int = 1, // V0 160 VlLogicRegs: Int = 1, // Vl 161 V0_IDX: Int = 0, 162 Vl_IDX: Int = 0, 163 NRPhyRegs: Int = 192, 164 VirtualLoadQueueSize: Int = 72, 165 LoadQueueRARSize: Int = 72, 166 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 167 RollbackGroupSize: Int = 8, 168 LoadQueueReplaySize: Int = 72, 169 LoadUncacheBufferSize: Int = 20, 170 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 171 StoreQueueSize: Int = 64, 172 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 173 StoreQueueForwardWithMask: Boolean = true, 174 VlsQueueSize: Int = 8, 175 RobSize: Int = 160, 176 RabSize: Int = 256, 177 VTypeBufferSize: Int = 64, // used to reorder vtype 178 IssueQueueSize: Int = 24, 179 IssueQueueCompEntrySize: Int = 16, 180 dpParams: DispatchParameters = DispatchParameters( 181 IntDqSize = 16, 182 FpDqSize = 16, 183 LsDqSize = 18, 184 IntDqDeqWidth = 8, 185 FpDqDeqWidth = 6, 186 VecDqDeqWidth = 6, 187 LsDqDeqWidth = 6, 188 ), 189 intPreg: PregParams = IntPregParams( 190 numEntries = 224, 191 numRead = None, 192 numWrite = None, 193 ), 194 fpPreg: PregParams = FpPregParams( 195 numEntries = 192, 196 numRead = None, 197 numWrite = None, 198 ), 199 vfPreg: VfPregParams = VfPregParams( 200 numEntries = 128, 201 numRead = None, 202 numWrite = None, 203 ), 204 v0Preg: V0PregParams = V0PregParams( 205 numEntries = 22, 206 numRead = None, 207 numWrite = None, 208 ), 209 vlPreg: VlPregParams = VlPregParams( 210 numEntries = 32, 211 numRead = None, 212 numWrite = None, 213 ), 214 IntRegCacheSize: Int = 16, 215 MemRegCacheSize: Int = 12, 216 intSchdVlWbPort: Int = 0, 217 vfSchdVlWbPort: Int = 1, 218 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 219 IfuRedirectNum: Int = 1, 220 LoadPipelineWidth: Int = 3, 221 StorePipelineWidth: Int = 2, 222 VecLoadPipelineWidth: Int = 2, 223 VecStorePipelineWidth: Int = 2, 224 VecMemSrcInWidth: Int = 2, 225 VecMemInstWbWidth: Int = 1, 226 VecMemDispatchWidth: Int = 1, 227 VecMemDispatchMaxNumber: Int = 16, 228 VecMemUnitStrideMaxFlowNum: Int = 2, 229 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 230 StoreBufferSize: Int = 16, 231 StoreBufferThreshold: Int = 7, 232 EnsbufferWidth: Int = 2, 233 LoadDependencyWidth: Int = 2, 234 // ============ VLSU ============ 235 VlMergeBufferSize: Int = 16, 236 VsMergeBufferSize: Int = 16, 237 UopWritebackWidth: Int = 2, 238 VLUopWritebackWidth: Int = 2, 239 VSUopWritebackWidth: Int = 1, 240 VSegmentBufferSize: Int = 8, 241 VFOFBufferSize: Int = 8, 242 VLFOFWritebackWidth: Int = 1, 243 // ============================== 244 UncacheBufferSize: Int = 4, 245 EnableLoadToLoadForward: Boolean = false, 246 EnableFastForward: Boolean = true, 247 EnableLdVioCheckAfterReset: Boolean = true, 248 EnableSoftPrefetchAfterReset: Boolean = true, 249 EnableCacheErrorAfterReset: Boolean = true, 250 EnableAccurateLoadError: Boolean = false, 251 EnableUncacheWriteOutstanding: Boolean = false, 252 EnableHardwareStoreMisalign: Boolean = true, 253 EnableHardwareLoadMisalign: Boolean = true, 254 EnableStorePrefetchAtIssue: Boolean = false, 255 EnableStorePrefetchAtCommit: Boolean = false, 256 EnableAtCommitMissTrigger: Boolean = true, 257 EnableStorePrefetchSMS: Boolean = false, 258 EnableStorePrefetchSPB: Boolean = false, 259 HasCMO: Boolean = true, 260 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 261 MMUVmidLen: Int = 14, 262 ReSelectLen: Int = 7, // load replay queue replay select counter len 263 iwpuParameters: WPUParameters = WPUParameters( 264 enWPU = false, 265 algoName = "mmru", 266 isICache = true, 267 ), 268 dwpuParameters: WPUParameters = WPUParameters( 269 enWPU = false, 270 algoName = "mmru", 271 enCfPred = false, 272 isICache = false, 273 ), 274 itlbParameters: TLBParameters = TLBParameters( 275 name = "itlb", 276 fetchi = true, 277 useDmode = false, 278 NWays = 48, 279 ), 280 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 281 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 282 ldtlbParameters: TLBParameters = TLBParameters( 283 name = "ldtlb", 284 NWays = 48, 285 outReplace = false, 286 partialStaticPMP = true, 287 outsideRecvFlush = true, 288 saveLevel = false, 289 lgMaxSize = 4 290 ), 291 sttlbParameters: TLBParameters = TLBParameters( 292 name = "sttlb", 293 NWays = 48, 294 outReplace = false, 295 partialStaticPMP = true, 296 outsideRecvFlush = true, 297 saveLevel = false, 298 lgMaxSize = 4 299 ), 300 hytlbParameters: TLBParameters = TLBParameters( 301 name = "hytlb", 302 NWays = 48, 303 outReplace = false, 304 partialStaticPMP = true, 305 outsideRecvFlush = true, 306 saveLevel = false, 307 lgMaxSize = 4 308 ), 309 pftlbParameters: TLBParameters = TLBParameters( 310 name = "pftlb", 311 NWays = 48, 312 outReplace = false, 313 partialStaticPMP = true, 314 outsideRecvFlush = true, 315 saveLevel = false, 316 lgMaxSize = 4 317 ), 318 l2ToL1tlbParameters: TLBParameters = TLBParameters( 319 name = "l2tlb", 320 NWays = 48, 321 outReplace = false, 322 partialStaticPMP = true, 323 outsideRecvFlush = true, 324 saveLevel = false 325 ), 326 refillBothTlb: Boolean = false, 327 btlbParameters: TLBParameters = TLBParameters( 328 name = "btlb", 329 NWays = 48, 330 ), 331 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 332 NumPerfCounters: Int = 16, 333 icacheParameters: ICacheParameters = ICacheParameters( 334 tagECC = Some("parity"), 335 dataECC = Some("parity"), 336 replacer = Some("setplru"), 337 ), 338 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 339 tagECC = Some("secded"), 340 dataECC = Some("secded"), 341 replacer = Some("setplru"), 342 nMissEntries = 16, 343 nProbeEntries = 8, 344 nReleaseEntries = 18, 345 nMaxPrefetchEntry = 6, 346 )), 347 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 348 name = "l2", 349 ways = 8, 350 sets = 1024, // default 512KB L2 351 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 352 coupledL2.prefetch.TPParameters()), 353 )), 354 L2NBanks: Int = 1, 355 usePTWRepeater: Boolean = false, 356 softTLB: Boolean = false, // dpi-c l1tlb debug only 357 softPTW: Boolean = false, // dpi-c l2tlb debug only 358 softPTWDelay: Int = 1 359){ 360 def vlWidth = log2Up(VLEN) + 1 361 362 /** 363 * the minimum element length of vector elements 364 */ 365 val minVecElen: Int = 8 366 367 /** 368 * the maximum number of elements in vector register 369 */ 370 val maxElemPerVreg: Int = VLEN / minVecElen 371 372 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 373 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 374 375 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 376 val RegCacheIdxWidth = log2Up(RegCacheSize) 377 378 val intSchdParams = { 379 implicit val schdType: SchedulerType = IntScheduler() 380 SchdBlockParams(Seq( 381 IssueBlockParams(Seq( 382 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 383 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 384 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 385 IssueBlockParams(Seq( 386 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 387 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 388 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 389 IssueBlockParams(Seq( 390 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 391 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 395 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 396 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 397 ), 398 numPregs = intPreg.numEntries, 399 numDeqOutside = 0, 400 schdType = schdType, 401 rfDataWidth = intPreg.dataCfg.dataWidth, 402 numUopIn = dpParams.IntDqDeqWidth, 403 ) 404 } 405 406 val fpSchdParams = { 407 implicit val schdType: SchedulerType = FpScheduler() 408 SchdBlockParams(Seq( 409 IssueBlockParams(Seq( 410 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 411 ), numEntries = 18, numEnq = 2, numComp = 16), 412 IssueBlockParams(Seq( 413 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 414 ), numEntries = 18, numEnq = 2, numComp = 16), 415 IssueBlockParams(Seq( 416 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 417 ), numEntries = 18, numEnq = 2, numComp = 16), 418 IssueBlockParams(Seq( 419 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 420 ), numEntries = 18, numEnq = 2, numComp = 16), 421 IssueBlockParams(Seq( 422 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 423 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 424 ), numEntries = 18, numEnq = 2, numComp = 16), 425 ), 426 numPregs = fpPreg.numEntries, 427 numDeqOutside = 0, 428 schdType = schdType, 429 rfDataWidth = fpPreg.dataCfg.dataWidth, 430 numUopIn = dpParams.FpDqDeqWidth, 431 ) 432 } 433 434 val vfSchdParams = { 435 implicit val schdType: SchedulerType = VfScheduler() 436 SchdBlockParams(Seq( 437 IssueBlockParams(Seq( 438 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 439 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 440 ), numEntries = 16, numEnq = 2, numComp = 14), 441 IssueBlockParams(Seq( 442 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 443 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 444 ), numEntries = 16, numEnq = 2, numComp = 14), 445 IssueBlockParams(Seq( 446 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 447 ), numEntries = 10, numEnq = 2, numComp = 8), 448 ), 449 numPregs = vfPreg.numEntries, 450 numDeqOutside = 0, 451 schdType = schdType, 452 rfDataWidth = vfPreg.dataCfg.dataWidth, 453 numUopIn = dpParams.VecDqDeqWidth, 454 ) 455 } 456 457 val memSchdParams = { 458 implicit val schdType: SchedulerType = MemScheduler() 459 val rfDataWidth = 64 460 461 SchdBlockParams(Seq( 462 IssueBlockParams(Seq( 463 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 464 ), numEntries = 16, numEnq = 1, numComp = 15), 465 IssueBlockParams(Seq( 466 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 467 ), numEntries = 16, numEnq = 1, numComp = 15), 468 IssueBlockParams(Seq( 469 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 470 ), numEntries = 16, numEnq = 1, numComp = 15), 471 IssueBlockParams(Seq( 472 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 473 ), numEntries = 16, numEnq = 1, numComp = 15), 474 IssueBlockParams(Seq( 475 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 476 ), numEntries = 16, numEnq = 1, numComp = 15), 477 IssueBlockParams(Seq( 478 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 479 ), numEntries = 16, numEnq = 1, numComp = 15), 480 IssueBlockParams(Seq( 481 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 482 ), numEntries = 16, numEnq = 1, numComp = 15), 483 IssueBlockParams(Seq( 484 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(12, 0)))), 485 ), numEntries = 16, numEnq = 1, numComp = 15), 486 IssueBlockParams(Seq( 487 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(13, 0)))), 488 ), numEntries = 16, numEnq = 1, numComp = 15), 489 ), 490 numPregs = intPreg.numEntries max vfPreg.numEntries, 491 numDeqOutside = 0, 492 schdType = schdType, 493 rfDataWidth = rfDataWidth, 494 numUopIn = dpParams.LsDqDeqWidth, 495 ) 496 } 497 498 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 499 500 def iqWakeUpParams = { 501 Seq( 502 WakeUpConfig( 503 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 504 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 505 ), 506 // TODO: add load -> fp slow wakeup 507 WakeUpConfig( 508 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 509 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 510 ), 511 WakeUpConfig( 512 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 513 Seq("STD0", "STD1") 514 ), 515// WakeUpConfig( 516// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 517// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 518// ), 519 ).flatten 520 } 521 522 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 523 524 val backendParams: BackendParams = backend.BackendParams( 525 Map( 526 IntScheduler() -> intSchdParams, 527 FpScheduler() -> fpSchdParams, 528 VfScheduler() -> vfSchdParams, 529 MemScheduler() -> memSchdParams, 530 ), 531 Seq( 532 intPreg, 533 fpPreg, 534 vfPreg, 535 v0Preg, 536 vlPreg, 537 fakeIntPreg 538 ), 539 iqWakeUpParams, 540 ) 541 542 // Parameters for trace extension. 543 // Trace parameters is useful for XSTOP. 544 val TraceGroupNum = 3 // Width to Encoder 545} 546 547case object DebugOptionsKey extends Field[DebugOptions] 548 549case class DebugOptions 550( 551 FPGAPlatform: Boolean = false, 552 ResetGen: Boolean = false, 553 EnableDifftest: Boolean = false, 554 AlwaysBasicDiff: Boolean = true, 555 EnableDebug: Boolean = false, 556 EnablePerfDebug: Boolean = true, 557 UseDRAMSim: Boolean = false, 558 EnableConstantin: Boolean = false, 559 EnableChiselDB: Boolean = false, 560 AlwaysBasicDB: Boolean = true, 561 EnableRollingDB: Boolean = false 562) 563 564trait HasXSParameter { 565 566 implicit val p: Parameters 567 568 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 569 def PmemRanges = p(SoCParamsKey).PmemRanges 570 def PmemLowBounds = PmemRanges.unzip._1 571 def PmemHighBounds = PmemRanges.unzip._2 572 final val PageOffsetWidth = 12 573 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 574 575 def coreParams = p(XSCoreParamsKey) 576 def env = p(DebugOptionsKey) 577 578 def XLEN = coreParams.XLEN 579 def VLEN = coreParams.VLEN 580 def ELEN = coreParams.ELEN 581 def HSXLEN = coreParams.HSXLEN 582 val minFLen = 32 583 val fLen = 64 584 def hartIdLen = p(MaxHartIdBits) 585 val xLen = XLEN 586 587 def HasMExtension = coreParams.HasMExtension 588 def HasCExtension = coreParams.HasCExtension 589 def HasHExtension = coreParams.HasHExtension 590 def EnableSv48 = coreParams.EnableSv48 591 def HasDiv = coreParams.HasDiv 592 def HasIcache = coreParams.HasICache 593 def HasDcache = coreParams.HasDCache 594 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 595 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 596 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 597 def GPAddrBits = { 598 if (EnableSv48) 599 coreParams.GPAddrBitsSv48x4 600 else 601 coreParams.GPAddrBitsSv39x4 602 } 603 def VAddrBits = { 604 if (HasHExtension) { 605 if (EnableSv48) 606 coreParams.GPAddrBitsSv48x4 607 else 608 coreParams.GPAddrBitsSv39x4 609 } else { 610 if (EnableSv48) 611 coreParams.VAddrBitsSv48 612 else 613 coreParams.VAddrBitsSv39 614 } 615 } // VAddrBits is Virtual Memory addr bits 616 617 def VAddrMaxBits = { 618 if(EnableSv48) { 619 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 620 } else { 621 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 622 } 623 } 624 625 def AsidLength = coreParams.AsidLength 626 def VmidLength = coreParams.VmidLength 627 def ReSelectLen = coreParams.ReSelectLen 628 def AddrBytes = AddrBits / 8 // unused 629 def DataBits = XLEN 630 def DataBytes = DataBits / 8 631 def VDataBytes = VLEN / 8 632 def HasFPU = coreParams.HasFPU 633 def HasVPU = coreParams.HasVPU 634 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 635 def FetchWidth = coreParams.FetchWidth 636 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 637 def EnableBPU = coreParams.EnableBPU 638 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 639 def EnableRAS = coreParams.EnableRAS 640 def EnableLB = coreParams.EnableLB 641 def EnableLoop = coreParams.EnableLoop 642 def EnableSC = coreParams.EnableSC 643 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 644 def HistoryLength = coreParams.HistoryLength 645 def EnableGHistDiff = coreParams.EnableGHistDiff 646 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 647 def EnableClockGate = coreParams.EnableClockGate 648 def UbtbGHRLength = coreParams.UbtbGHRLength 649 def UbtbSize = coreParams.UbtbSize 650 def EnableFauFTB = coreParams.EnableFauFTB 651 def FtbSize = coreParams.FtbSize 652 def FtbWays = coreParams.FtbWays 653 def RasSize = coreParams.RasSize 654 def RasSpecSize = coreParams.RasSpecSize 655 def RasCtrSize = coreParams.RasCtrSize 656 657 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 658 coreParams.branchPredictor(resp_in, p) 659 } 660 def numBr = coreParams.numBr 661 def TageTableInfos = coreParams.TageTableInfos 662 def TageBanks = coreParams.numBr 663 def SCNRows = coreParams.SCNRows 664 def SCCtrBits = coreParams.SCCtrBits 665 def SCHistLens = coreParams.SCHistLens 666 def SCNTables = coreParams.SCNTables 667 668 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 669 case ((n, cb), h) => (n, cb, h) 670 } 671 def ITTageTableInfos = coreParams.ITTageTableInfos 672 type FoldedHistoryInfo = Tuple2[Int, Int] 673 def foldedGHistInfos = 674 (TageTableInfos.map{ case (nRows, h, t) => 675 if (h > 0) 676 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 677 else 678 Set[FoldedHistoryInfo]() 679 }.reduce(_++_).toSet ++ 680 SCTableInfos.map{ case (nRows, _, h) => 681 if (h > 0) 682 Set((h, min(log2Ceil(nRows/TageBanks), h))) 683 else 684 Set[FoldedHistoryInfo]() 685 }.reduce(_++_).toSet ++ 686 ITTageTableInfos.map{ case (nRows, h, t) => 687 if (h > 0) 688 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 689 else 690 Set[FoldedHistoryInfo]() 691 }.reduce(_++_) ++ 692 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 693 ).toList 694 695 696 697 def CacheLineSize = coreParams.CacheLineSize 698 def CacheLineHalfWord = CacheLineSize / 16 699 def ExtHistoryLength = HistoryLength + 64 700 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 701 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 702 def IBufSize = coreParams.IBufSize 703 def IBufNBank = coreParams.IBufNBank 704 def backendParams: BackendParams = coreParams.backendParams 705 def DecodeWidth = coreParams.DecodeWidth 706 def RenameWidth = coreParams.RenameWidth 707 def CommitWidth = coreParams.CommitWidth 708 def RobCommitWidth = coreParams.RobCommitWidth 709 def RabCommitWidth = coreParams.RabCommitWidth 710 def MaxUopSize = coreParams.MaxUopSize 711 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 712 def RenameSnapshotNum = coreParams.RenameSnapshotNum 713 def FtqSize = coreParams.FtqSize 714 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 715 def IntLogicRegs = coreParams.IntLogicRegs 716 def FpLogicRegs = coreParams.FpLogicRegs 717 def VecLogicRegs = coreParams.VecLogicRegs 718 def V0LogicRegs = coreParams.V0LogicRegs 719 def VlLogicRegs = coreParams.VlLogicRegs 720 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 721 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 722 def V0_IDX = coreParams.V0_IDX 723 def Vl_IDX = coreParams.Vl_IDX 724 def IntPhyRegs = coreParams.intPreg.numEntries 725 def FpPhyRegs = coreParams.fpPreg.numEntries 726 def VfPhyRegs = coreParams.vfPreg.numEntries 727 def V0PhyRegs = coreParams.v0Preg.numEntries 728 def VlPhyRegs = coreParams.vlPreg.numEntries 729 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 730 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 731 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 732 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 733 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 734 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 735 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 736 def RobSize = coreParams.RobSize 737 def RabSize = coreParams.RabSize 738 def VTypeBufferSize = coreParams.VTypeBufferSize 739 def IntRegCacheSize = coreParams.IntRegCacheSize 740 def MemRegCacheSize = coreParams.MemRegCacheSize 741 def RegCacheSize = coreParams.RegCacheSize 742 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 743 /** 744 * the minimum element length of vector elements 745 */ 746 def minVecElen: Int = coreParams.minVecElen 747 748 /** 749 * the maximum number of elements in vector register 750 */ 751 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 752 753 def IntRefCounterWidth = log2Ceil(RobSize) 754 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 755 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 756 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 757 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 758 def LoadQueueRARSize = coreParams.LoadQueueRARSize 759 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 760 def RollbackGroupSize = coreParams.RollbackGroupSize 761 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 762 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 763 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 764 def StoreQueueSize = coreParams.StoreQueueSize 765 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 766 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 767 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 768 def VlsQueueSize = coreParams.VlsQueueSize 769 def dpParams = coreParams.dpParams 770 771 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 772 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 773 774 def NumRedirect = backendParams.numRedirect 775 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 776 def FtqRedirectAheadNum = NumRedirect 777 def IfuRedirectNum = coreParams.IfuRedirectNum 778 def LoadPipelineWidth = coreParams.LoadPipelineWidth 779 def StorePipelineWidth = coreParams.StorePipelineWidth 780 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 781 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 782 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 783 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 784 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 785 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 786 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 787 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 788 def StoreBufferSize = coreParams.StoreBufferSize 789 def StoreBufferThreshold = coreParams.StoreBufferThreshold 790 def EnsbufferWidth = coreParams.EnsbufferWidth 791 def LoadDependencyWidth = coreParams.LoadDependencyWidth 792 def VlMergeBufferSize = coreParams.VlMergeBufferSize 793 def VsMergeBufferSize = coreParams.VsMergeBufferSize 794 def UopWritebackWidth = coreParams.UopWritebackWidth 795 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 796 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 797 def VSegmentBufferSize = coreParams.VSegmentBufferSize 798 def VFOFBufferSize = coreParams.VFOFBufferSize 799 def UncacheBufferSize = coreParams.UncacheBufferSize 800 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 801 def EnableFastForward = coreParams.EnableFastForward 802 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 803 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 804 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 805 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 806 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 807 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 808 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 809 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 810 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 811 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 812 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 813 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 814 def HasCMO = coreParams.HasCMO && p(EnableCHI) 815 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 816 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 817 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 818 def asidLen = coreParams.MMUAsidLen 819 def vmidLen = coreParams.MMUVmidLen 820 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 821 def refillBothTlb = coreParams.refillBothTlb 822 def iwpuParam = coreParams.iwpuParameters 823 def dwpuParam = coreParams.dwpuParameters 824 def itlbParams = coreParams.itlbParameters 825 def ldtlbParams = coreParams.ldtlbParameters 826 def sttlbParams = coreParams.sttlbParameters 827 def hytlbParams = coreParams.hytlbParameters 828 def pftlbParams = coreParams.pftlbParameters 829 def l2ToL1Params = coreParams.l2ToL1tlbParameters 830 def btlbParams = coreParams.btlbParameters 831 def l2tlbParams = coreParams.l2tlbParameters 832 def NumPerfCounters = coreParams.NumPerfCounters 833 834 def instBytes = if (HasCExtension) 2 else 4 835 def instOffsetBits = log2Ceil(instBytes) 836 837 def icacheParameters = coreParams.icacheParameters 838 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 839 840 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 841 // for constrained LR/SC loop 842 def LRSCCycles = 64 843 // for lr storm 844 def LRSCBackOff = 8 845 846 // cache hierarchy configurations 847 def l1BusDataWidth = 256 848 849 // load violation predict 850 def ResetTimeMax2Pow = 20 //1078576 851 def ResetTimeMin2Pow = 10 //1024 852 // wait table parameters 853 def WaitTableSize = 1024 854 def MemPredPCWidth = log2Up(WaitTableSize) 855 def LWTUse2BitCounter = true 856 // store set parameters 857 def SSITSize = WaitTableSize 858 def LFSTSize = 32 859 def SSIDWidth = log2Up(LFSTSize) 860 def LFSTWidth = 4 861 def StoreSetEnable = true // LWT will be disabled if SS is enabled 862 def LFSTEnable = true 863 864 def PCntIncrStep: Int = 6 865 def numPCntHc: Int = 12 866 def numPCntPtw: Int = 19 867 868 def numCSRPCntFrontend = 8 869 def numCSRPCntCtrl = 8 870 def numCSRPCntLsu = 8 871 def numCSRPCntHc = 5 872 def printEventCoding = true 873 def printCriticalError = false 874 def maxCommitStuck = pow(2, 21).toInt 875 876 // Vector load exception 877 def maxMergeNumPerCycle = 4 878 879 // Parameters for Sdtrig extension 880 protected def TriggerNum = 4 881 protected def TriggerChainMaxLength = 2 882 883 // Parameters for Trace extension 884 def TraceGroupNum = coreParams.TraceGroupNum 885} 886