1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.backend.trace._ 33import xiangshan.cache.DCacheParameters 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import coupledL2.tl2chi._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.{max, min, pow} 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 PAddrBitsMax: Int = 56, // The bits of physical address from Sv39/Sv48/Sv57 virtual address translation. 72 VAddrBitsSv39: Int = 39, 73 GPAddrBitsSv39x4: Int = 41, 74 VAddrBitsSv48: Int = 48, 75 GPAddrBitsSv48x4: Int = 50, 76 HasFPU: Boolean = true, 77 HasVPU: Boolean = true, 78 HasCustomCSRCacheOp: Boolean = true, 79 FetchWidth: Int = 8, 80 AsidLength: Int = 16, 81 VmidLength: Int = 14, 82 EnableBPU: Boolean = true, 83 EnableBPD: Boolean = true, 84 EnableRAS: Boolean = true, 85 EnableLB: Boolean = false, 86 EnableLoop: Boolean = true, 87 EnableSC: Boolean = true, 88 EnbaleTlbDebug: Boolean = false, 89 EnableClockGate: Boolean = true, 90 EnableJal: Boolean = false, 91 EnableFauFTB: Boolean = true, 92 EnableSv48: Boolean = true, 93 UbtbGHRLength: Int = 4, 94 // HistoryLength: Int = 512, 95 EnableGHistDiff: Boolean = true, 96 EnableCommitGHistDiff: Boolean = true, 97 UbtbSize: Int = 256, 98 FtbSize: Int = 2048, 99 FtbWays: Int = 4, 100 FtbTagLength: Int = 20, 101 RasSize: Int = 16, 102 RasSpecSize: Int = 32, 103 RasCtrSize: Int = 3, 104 CacheLineSize: Int = 512, 105 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 4096, 8, 8), 108 ( 4096, 13, 8), 109 ( 4096, 32, 8), 110 ( 4096, 119, 8)), 111 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 112 // Sets Hist Tag 113 Seq(( 256, 4, 9), 114 ( 256, 8, 9), 115 ( 512, 13, 9), 116 ( 512, 16, 9), 117 ( 512, 32, 9)), 118 SCNRows: Int = 512, 119 SCNTables: Int = 4, 120 SCCtrBits: Int = 6, 121 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 122 numBr: Int = 2, 123 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 124 (resp_in: BranchPredictionResp, p: Parameters) => { 125 val ftb = Module(new FTB()(p)) 126 val uftb = Module(new FauFTB()(p)) 127 val tage = Module(new Tage_SC()(p)) 128 val ras = Module(new RAS()(p)) 129 val ittage = Module(new ITTage()(p)) 130 val preds = Seq(uftb, tage, ftb, ittage, ras) 131 preds.map(_.io := DontCare) 132 133 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 134 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 135 136 uftb.io.in.bits.resp_in(0) := resp_in 137 tage.io.in.bits.resp_in(0) := uftb.io.out 138 ftb.io.in.bits.resp_in(0) := tage.io.out 139 ittage.io.in.bits.resp_in(0) := ftb.io.out 140 ras.io.in.bits.resp_in(0) := ittage.io.out 141 142 (preds, ras.io.out) 143 }, 144 ICacheForceMetaECCError: Boolean = false, 145 ICacheForceDataECCError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 8, 151 RobCommitWidth: Int = 8, 152 RabCommitWidth: Int = 6, 153 MaxUopSize: Int = 65, 154 EnableRenameSnapshot: Boolean = true, 155 RenameSnapshotNum: Int = 4, 156 FtqSize: Int = 64, 157 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 158 IntLogicRegs: Int = 32, 159 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 160 VecLogicRegs: Int = 32 + 15, // 15: tmp 161 V0LogicRegs: Int = 1, // V0 162 VlLogicRegs: Int = 1, // Vl 163 V0_IDX: Int = 0, 164 Vl_IDX: Int = 0, 165 NRPhyRegs: Int = 192, 166 VirtualLoadQueueSize: Int = 72, 167 LoadQueueRARSize: Int = 72, 168 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 169 RollbackGroupSize: Int = 8, 170 LoadQueueReplaySize: Int = 72, 171 LoadUncacheBufferSize: Int = 20, 172 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 173 StoreQueueSize: Int = 64, 174 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 175 StoreQueueForwardWithMask: Boolean = true, 176 VlsQueueSize: Int = 8, 177 RobSize: Int = 160, 178 RabSize: Int = 256, 179 VTypeBufferSize: Int = 64, // used to reorder vtype 180 IssueQueueSize: Int = 24, 181 IssueQueueCompEntrySize: Int = 16, 182 dpParams: DispatchParameters = DispatchParameters( 183 IntDqSize = 16, 184 FpDqSize = 16, 185 LsDqSize = 18, 186 IntDqDeqWidth = 8, 187 FpDqDeqWidth = 6, 188 VecDqDeqWidth = 6, 189 LsDqDeqWidth = 6, 190 ), 191 intPreg: PregParams = IntPregParams( 192 numEntries = 224, 193 numRead = None, 194 numWrite = None, 195 ), 196 fpPreg: PregParams = FpPregParams( 197 numEntries = 192, 198 numRead = None, 199 numWrite = None, 200 ), 201 vfPreg: VfPregParams = VfPregParams( 202 numEntries = 128, 203 numRead = None, 204 numWrite = None, 205 ), 206 v0Preg: V0PregParams = V0PregParams( 207 numEntries = 22, 208 numRead = None, 209 numWrite = None, 210 ), 211 vlPreg: VlPregParams = VlPregParams( 212 numEntries = 32, 213 numRead = None, 214 numWrite = None, 215 ), 216 IntRegCacheSize: Int = 16, 217 MemRegCacheSize: Int = 12, 218 intSchdVlWbPort: Int = 0, 219 vfSchdVlWbPort: Int = 1, 220 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 221 IfuRedirectNum: Int = 1, 222 LoadPipelineWidth: Int = 3, 223 StorePipelineWidth: Int = 2, 224 VecLoadPipelineWidth: Int = 2, 225 VecStorePipelineWidth: Int = 2, 226 VecMemSrcInWidth: Int = 2, 227 VecMemInstWbWidth: Int = 1, 228 VecMemDispatchWidth: Int = 1, 229 VecMemDispatchMaxNumber: Int = 16, 230 VecMemUnitStrideMaxFlowNum: Int = 2, 231 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 232 StoreBufferSize: Int = 16, 233 StoreBufferThreshold: Int = 7, 234 EnsbufferWidth: Int = 2, 235 LoadDependencyWidth: Int = 2, 236 // ============ VLSU ============ 237 VlMergeBufferSize: Int = 16, 238 VsMergeBufferSize: Int = 16, 239 UopWritebackWidth: Int = 2, 240 VLUopWritebackWidth: Int = 2, 241 VSUopWritebackWidth: Int = 1, 242 VSegmentBufferSize: Int = 8, 243 VFOFBufferSize: Int = 8, 244 VLFOFWritebackWidth: Int = 1, 245 // ============================== 246 UncacheBufferSize: Int = 4, 247 EnableLoadToLoadForward: Boolean = false, 248 EnableFastForward: Boolean = true, 249 EnableLdVioCheckAfterReset: Boolean = true, 250 EnableSoftPrefetchAfterReset: Boolean = true, 251 EnableCacheErrorAfterReset: Boolean = true, 252 EnableAccurateLoadError: Boolean = false, 253 EnableUncacheWriteOutstanding: Boolean = false, 254 EnableHardwareStoreMisalign: Boolean = true, 255 EnableHardwareLoadMisalign: Boolean = true, 256 EnableStorePrefetchAtIssue: Boolean = false, 257 EnableStorePrefetchAtCommit: Boolean = false, 258 EnableAtCommitMissTrigger: Boolean = true, 259 EnableStorePrefetchSMS: Boolean = false, 260 EnableStorePrefetchSPB: Boolean = false, 261 HasCMO: Boolean = true, 262 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 263 MMUVmidLen: Int = 14, 264 ReSelectLen: Int = 7, // load replay queue replay select counter len 265 iwpuParameters: WPUParameters = WPUParameters( 266 enWPU = false, 267 algoName = "mmru", 268 isICache = true, 269 ), 270 dwpuParameters: WPUParameters = WPUParameters( 271 enWPU = false, 272 algoName = "mmru", 273 enCfPred = false, 274 isICache = false, 275 ), 276 itlbParameters: TLBParameters = TLBParameters( 277 name = "itlb", 278 fetchi = true, 279 useDmode = false, 280 NWays = 48, 281 ), 282 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 283 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 284 ldtlbParameters: TLBParameters = TLBParameters( 285 name = "ldtlb", 286 NWays = 48, 287 outReplace = false, 288 partialStaticPMP = true, 289 outsideRecvFlush = true, 290 saveLevel = false, 291 lgMaxSize = 4 292 ), 293 sttlbParameters: TLBParameters = TLBParameters( 294 name = "sttlb", 295 NWays = 48, 296 outReplace = false, 297 partialStaticPMP = true, 298 outsideRecvFlush = true, 299 saveLevel = false, 300 lgMaxSize = 4 301 ), 302 hytlbParameters: TLBParameters = TLBParameters( 303 name = "hytlb", 304 NWays = 48, 305 outReplace = false, 306 partialStaticPMP = true, 307 outsideRecvFlush = true, 308 saveLevel = false, 309 lgMaxSize = 4 310 ), 311 pftlbParameters: TLBParameters = TLBParameters( 312 name = "pftlb", 313 NWays = 48, 314 outReplace = false, 315 partialStaticPMP = true, 316 outsideRecvFlush = true, 317 saveLevel = false, 318 lgMaxSize = 4 319 ), 320 l2ToL1tlbParameters: TLBParameters = TLBParameters( 321 name = "l2tlb", 322 NWays = 48, 323 outReplace = false, 324 partialStaticPMP = true, 325 outsideRecvFlush = true, 326 saveLevel = false 327 ), 328 refillBothTlb: Boolean = false, 329 btlbParameters: TLBParameters = TLBParameters( 330 name = "btlb", 331 NWays = 48, 332 ), 333 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 334 NumPerfCounters: Int = 16, 335 icacheParameters: ICacheParameters = ICacheParameters( 336 tagECC = Some("parity"), 337 dataECC = Some("parity"), 338 replacer = Some("setplru"), 339 ), 340 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 341 tagECC = Some("secded"), 342 dataECC = Some("secded"), 343 replacer = Some("setplru"), 344 nMissEntries = 16, 345 nProbeEntries = 8, 346 nReleaseEntries = 18, 347 nMaxPrefetchEntry = 6, 348 enableTagEcc = true, 349 enableDataEcc = true, 350 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 351 )), 352 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 353 name = "l2", 354 ways = 8, 355 sets = 1024, // default 512KB L2 356 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 357 coupledL2.prefetch.TPParameters()), 358 )), 359 L2NBanks: Int = 1, 360 usePTWRepeater: Boolean = false, 361 softTLB: Boolean = false, // dpi-c l1tlb debug only 362 softPTW: Boolean = false, // dpi-c l2tlb debug only 363 softPTWDelay: Int = 1 364){ 365 def ISABase = "rv64i" 366 def ISAExtensions = Seq( 367 // single letter extensions, in canonical order 368 "i", "m", "a", "f", "d", "c", /* "b", */ "v", "h", 369 // multi-letter extensions, sorted alphanumerically 370 "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", 371 "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", 372 "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", 373 "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", 374 "sv48", "svade", "svbare", "svinval", "svpbmt", "za64rs", "zacas", "zba", "zbb", "zbc", "zbkb", 375 "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", 376 "zicboz", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", 377 "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", 378 "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b" 379 ) 380 381 def vlWidth = log2Up(VLEN) + 1 382 383 /** 384 * the minimum element length of vector elements 385 */ 386 val minVecElen: Int = 8 387 388 /** 389 * the maximum number of elements in vector register 390 */ 391 val maxElemPerVreg: Int = VLEN / minVecElen 392 393 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 394 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 395 396 val RegCacheSize = IntRegCacheSize + MemRegCacheSize 397 val RegCacheIdxWidth = log2Up(RegCacheSize) 398 399 val intSchdParams = { 400 implicit val schdType: SchedulerType = IntScheduler() 401 SchdBlockParams(Seq( 402 IssueBlockParams(Seq( 403 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 404 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1))), true, 2), 405 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 406 IssueBlockParams(Seq( 407 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 408 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1))), true, 2), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 IssueBlockParams(Seq( 411 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 412 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = intSchdVlWbPort, 0), FpWB(port = 2, 1)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 413 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 414 IssueBlockParams(Seq( 415 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 416 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 417 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 418 ), 419 numPregs = intPreg.numEntries, 420 numDeqOutside = 0, 421 schdType = schdType, 422 rfDataWidth = intPreg.dataCfg.dataWidth, 423 numUopIn = dpParams.IntDqDeqWidth, 424 ) 425 } 426 427 val fpSchdParams = { 428 implicit val schdType: SchedulerType = FpScheduler() 429 SchdBlockParams(Seq( 430 IssueBlockParams(Seq( 431 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 432 ExeUnitParams("FEX1", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 433 ), numEntries = 18, numEnq = 2, numComp = 16), 434 IssueBlockParams(Seq( 435 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 436 ExeUnitParams("FEX3", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(9, 1)))), 437 ), numEntries = 18, numEnq = 2, numComp = 16), 438 IssueBlockParams(Seq( 439 ExeUnitParams("FEX4", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 1)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 440 ), numEntries = 18, numEnq = 2, numComp = 16), 441 ), 442 numPregs = fpPreg.numEntries, 443 numDeqOutside = 0, 444 schdType = schdType, 445 rfDataWidth = fpPreg.dataCfg.dataWidth, 446 numUopIn = dpParams.FpDqDeqWidth, 447 ) 448 } 449 450 val vfSchdParams = { 451 implicit val schdType: SchedulerType = VfScheduler() 452 SchdBlockParams(Seq( 453 IssueBlockParams(Seq( 454 ExeUnitParams("VFEX0", Seq(VialuCfg, VfaluCfg, VfmaCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0), VlWB(port = vfSchdVlWbPort, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 455 ExeUnitParams("VFEX1", Seq(VfcvtCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 2, 1), V0WB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 456 ), numEntries = 18, numEnq = 2, numComp = 14), 457 IssueBlockParams(Seq( 458 ExeUnitParams("VFEX2", Seq(VialuCfg, VfaluCfg, VfmaCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 459 ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 2, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 460 ), numEntries = 18, numEnq = 2, numComp = 14), 461 ), 462 numPregs = vfPreg.numEntries, 463 numDeqOutside = 0, 464 schdType = schdType, 465 rfDataWidth = vfPreg.dataCfg.dataWidth, 466 numUopIn = dpParams.VecDqDeqWidth, 467 ) 468 } 469 470 val memSchdParams = { 471 implicit val schdType: SchedulerType = MemScheduler() 472 val rfDataWidth = 64 473 474 SchdBlockParams(Seq( 475 IssueBlockParams(Seq( 476 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(7, 2)))), 477 ), numEntries = 16, numEnq = 2, numComp = 14), 478 IssueBlockParams(Seq( 479 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(6, 2)))), 480 ), numEntries = 16, numEnq = 2, numComp = 14), 481 IssueBlockParams(Seq( 482 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(3, 0)), Seq(Seq(IntRD(8, 0))), true, 2), 483 ), numEntries = 16, numEnq = 2, numComp = 14), 484 IssueBlockParams(Seq( 485 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(4, 0)), Seq(Seq(IntRD(9, 0))), true, 2), 486 ), numEntries = 16, numEnq = 2, numComp = 14), 487 IssueBlockParams(Seq( 488 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(5, 0)), Seq(Seq(IntRD(10, 0))), true, 2), 489 ), numEntries = 16, numEnq = 2, numComp = 14), 490 IssueBlockParams(Seq( 491 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0), VlWB(port = 2, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 492 ), numEntries = 16, numEnq = 2, numComp = 14), 493 IssueBlockParams(Seq( 494 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0), VlWB(port = 3, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 495 ), numEntries = 16, numEnq = 2, numComp = 14), 496 IssueBlockParams(Seq( 497 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(5, 2), FpRD(9, 0)))), 498 ), numEntries = 16, numEnq = 2, numComp = 14), 499 IssueBlockParams(Seq( 500 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(3, 2), FpRD(10, 0)))), 501 ), numEntries = 16, numEnq = 2, numComp = 14), 502 ), 503 numPregs = intPreg.numEntries max vfPreg.numEntries, 504 numDeqOutside = 0, 505 schdType = schdType, 506 rfDataWidth = rfDataWidth, 507 numUopIn = dpParams.LsDqDeqWidth, 508 ) 509 } 510 511 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 512 513 def iqWakeUpParams = { 514 Seq( 515 WakeUpConfig( 516 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 517 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 518 ), 519 // TODO: add load -> fp slow wakeup 520 WakeUpConfig( 521 Seq("FEX0", "FEX2", "FEX4") -> 522 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4") 523 ), 524 ).flatten 525 } 526 527 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 528 529 val backendParams: BackendParams = backend.BackendParams( 530 Map( 531 IntScheduler() -> intSchdParams, 532 FpScheduler() -> fpSchdParams, 533 VfScheduler() -> vfSchdParams, 534 MemScheduler() -> memSchdParams, 535 ), 536 Seq( 537 intPreg, 538 fpPreg, 539 vfPreg, 540 v0Preg, 541 vlPreg, 542 fakeIntPreg 543 ), 544 iqWakeUpParams, 545 ) 546 547 // Parameters for trace extension. 548 // Trace parameters is useful for XSTOP. 549 val traceParams: TraceParams = new TraceParams( 550 TraceGroupNum = 3, 551 IaddrWidth = GPAddrBitsSv48x4, 552 PrivWidth = 3, 553 ItypeWidth = 4, 554 IlastsizeWidth = 1, 555 ) 556} 557 558case object DebugOptionsKey extends Field[DebugOptions] 559 560case class DebugOptions 561( 562 FPGAPlatform: Boolean = false, 563 ResetGen: Boolean = false, 564 EnableDifftest: Boolean = false, 565 AlwaysBasicDiff: Boolean = true, 566 EnableDebug: Boolean = false, 567 EnablePerfDebug: Boolean = true, 568 UseDRAMSim: Boolean = false, 569 EnableConstantin: Boolean = false, 570 EnableChiselDB: Boolean = false, 571 AlwaysBasicDB: Boolean = true, 572 EnableRollingDB: Boolean = false 573) 574 575trait HasXSParameter { 576 577 implicit val p: Parameters 578 579 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 580 def PmemRanges = p(SoCParamsKey).PmemRanges 581 def PmemLowBounds = PmemRanges.unzip._1 582 def PmemHighBounds = PmemRanges.unzip._2 583 final val PageOffsetWidth = 12 584 def NodeIDWidth = p(SoCParamsKey).NodeIDWidthList(p(CHIIssue)) // NodeID width among NoC 585 586 def coreParams = p(XSCoreParamsKey) 587 def env = p(DebugOptionsKey) 588 589 def ISABase = coreParams.ISABase 590 def ISAExtensions = coreParams.ISAExtensions 591 def XLEN = coreParams.XLEN 592 def VLEN = coreParams.VLEN 593 def ELEN = coreParams.ELEN 594 def HSXLEN = coreParams.HSXLEN 595 val minFLen = 32 596 val fLen = 64 597 def hartIdLen = p(MaxHartIdBits) 598 val xLen = XLEN 599 600 def HasMExtension = coreParams.HasMExtension 601 def HasCExtension = coreParams.HasCExtension 602 def HasHExtension = coreParams.HasHExtension 603 def EnableSv48 = coreParams.EnableSv48 604 def HasDiv = coreParams.HasDiv 605 def HasIcache = coreParams.HasICache 606 def HasDcache = coreParams.HasDCache 607 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 608 def PAddrBitsMax = coreParams.PAddrBitsMax 609 def GPAddrBitsSv39x4 = coreParams.GPAddrBitsSv39x4 610 def GPAddrBitsSv48x4 = coreParams.GPAddrBitsSv48x4 611 def GPAddrBits = { 612 if (EnableSv48) 613 coreParams.GPAddrBitsSv48x4 614 else 615 coreParams.GPAddrBitsSv39x4 616 } 617 def VAddrBits = { 618 if (HasHExtension) { 619 if (EnableSv48) 620 coreParams.GPAddrBitsSv48x4 621 else 622 coreParams.GPAddrBitsSv39x4 623 } else { 624 if (EnableSv48) 625 coreParams.VAddrBitsSv48 626 else 627 coreParams.VAddrBitsSv39 628 } 629 } // VAddrBits is Virtual Memory addr bits 630 631 def VAddrMaxBits = { 632 if(EnableSv48) { 633 coreParams.VAddrBitsSv48 max coreParams.GPAddrBitsSv48x4 634 } else { 635 coreParams.VAddrBitsSv39 max coreParams.GPAddrBitsSv39x4 636 } 637 } 638 639 def AsidLength = coreParams.AsidLength 640 def VmidLength = coreParams.VmidLength 641 def ReSelectLen = coreParams.ReSelectLen 642 def AddrBytes = AddrBits / 8 // unused 643 def DataBits = XLEN 644 def DataBytes = DataBits / 8 645 def QuadWordBits = DataBits * 2 646 def QuadWordBytes = QuadWordBits / 8 647 def VDataBytes = VLEN / 8 648 def HasFPU = coreParams.HasFPU 649 def HasVPU = coreParams.HasVPU 650 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 651 def FetchWidth = coreParams.FetchWidth 652 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 653 def EnableBPU = coreParams.EnableBPU 654 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 655 def EnableRAS = coreParams.EnableRAS 656 def EnableLB = coreParams.EnableLB 657 def EnableLoop = coreParams.EnableLoop 658 def EnableSC = coreParams.EnableSC 659 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 660 def HistoryLength = coreParams.HistoryLength 661 def EnableGHistDiff = coreParams.EnableGHistDiff 662 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 663 def EnableClockGate = coreParams.EnableClockGate 664 def UbtbGHRLength = coreParams.UbtbGHRLength 665 def UbtbSize = coreParams.UbtbSize 666 def EnableFauFTB = coreParams.EnableFauFTB 667 def FtbSize = coreParams.FtbSize 668 def FtbWays = coreParams.FtbWays 669 def FtbTagLength = coreParams.FtbTagLength 670 def RasSize = coreParams.RasSize 671 def RasSpecSize = coreParams.RasSpecSize 672 def RasCtrSize = coreParams.RasCtrSize 673 674 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 675 coreParams.branchPredictor(resp_in, p) 676 } 677 def numBr = coreParams.numBr 678 def TageTableInfos = coreParams.TageTableInfos 679 def TageBanks = coreParams.numBr 680 def SCNRows = coreParams.SCNRows 681 def SCCtrBits = coreParams.SCCtrBits 682 def SCHistLens = coreParams.SCHistLens 683 def SCNTables = coreParams.SCNTables 684 685 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 686 case ((n, cb), h) => (n, cb, h) 687 } 688 def ITTageTableInfos = coreParams.ITTageTableInfos 689 type FoldedHistoryInfo = Tuple2[Int, Int] 690 def foldedGHistInfos = 691 (TageTableInfos.map{ case (nRows, h, t) => 692 if (h > 0) 693 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 694 else 695 Set[FoldedHistoryInfo]() 696 }.reduce(_++_).toSet ++ 697 SCTableInfos.map{ case (nRows, _, h) => 698 if (h > 0) 699 Set((h, min(log2Ceil(nRows/TageBanks), h))) 700 else 701 Set[FoldedHistoryInfo]() 702 }.reduce(_++_).toSet ++ 703 ITTageTableInfos.map{ case (nRows, h, t) => 704 if (h > 0) 705 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 706 else 707 Set[FoldedHistoryInfo]() 708 }.reduce(_++_) ++ 709 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 710 ).toList 711 712 713 714 def CacheLineSize = coreParams.CacheLineSize 715 def CacheLineHalfWord = CacheLineSize / 16 716 def ExtHistoryLength = HistoryLength + 64 717 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 718 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 719 def IBufSize = coreParams.IBufSize 720 def IBufNBank = coreParams.IBufNBank 721 def backendParams: BackendParams = coreParams.backendParams 722 def DecodeWidth = coreParams.DecodeWidth 723 def RenameWidth = coreParams.RenameWidth 724 def CommitWidth = coreParams.CommitWidth 725 def RobCommitWidth = coreParams.RobCommitWidth 726 def RabCommitWidth = coreParams.RabCommitWidth 727 def MaxUopSize = coreParams.MaxUopSize 728 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 729 def RenameSnapshotNum = coreParams.RenameSnapshotNum 730 def FtqSize = coreParams.FtqSize 731 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 732 def IntLogicRegs = coreParams.IntLogicRegs 733 def FpLogicRegs = coreParams.FpLogicRegs 734 def VecLogicRegs = coreParams.VecLogicRegs 735 def V0LogicRegs = coreParams.V0LogicRegs 736 def VlLogicRegs = coreParams.VlLogicRegs 737 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 738 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 739 def V0_IDX = coreParams.V0_IDX 740 def Vl_IDX = coreParams.Vl_IDX 741 def IntPhyRegs = coreParams.intPreg.numEntries 742 def FpPhyRegs = coreParams.fpPreg.numEntries 743 def VfPhyRegs = coreParams.vfPreg.numEntries 744 def V0PhyRegs = coreParams.v0Preg.numEntries 745 def VlPhyRegs = coreParams.vlPreg.numEntries 746 def MaxPhyRegs = Seq(IntPhyRegs, FpPhyRegs, VfPhyRegs, V0PhyRegs, VlPhyRegs).max 747 def IntPhyRegIdxWidth = log2Up(IntPhyRegs) 748 def FpPhyRegIdxWidth = log2Up(FpPhyRegs) 749 def VfPhyRegIdxWidth = log2Up(VfPhyRegs) 750 def V0PhyRegIdxWidth = log2Up(V0PhyRegs) 751 def VlPhyRegIdxWidth = log2Up(VlPhyRegs) 752 def PhyRegIdxWidth = Seq(IntPhyRegIdxWidth, FpPhyRegIdxWidth, VfPhyRegIdxWidth, V0PhyRegIdxWidth, VlPhyRegIdxWidth).max 753 def RobSize = coreParams.RobSize 754 def RabSize = coreParams.RabSize 755 def VTypeBufferSize = coreParams.VTypeBufferSize 756 def IntRegCacheSize = coreParams.IntRegCacheSize 757 def MemRegCacheSize = coreParams.MemRegCacheSize 758 def RegCacheSize = coreParams.RegCacheSize 759 def RegCacheIdxWidth = coreParams.RegCacheIdxWidth 760 /** 761 * the minimum element length of vector elements 762 */ 763 def minVecElen: Int = coreParams.minVecElen 764 765 /** 766 * the maximum number of elements in vector register 767 */ 768 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 769 770 def IntRefCounterWidth = log2Ceil(RobSize) 771 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 772 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 773 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 774 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 775 def LoadQueueRARSize = coreParams.LoadQueueRARSize 776 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 777 def RollbackGroupSize = coreParams.RollbackGroupSize 778 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 779 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 780 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 781 def StoreQueueSize = coreParams.StoreQueueSize 782 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 783 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 784 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 785 def VlsQueueSize = coreParams.VlsQueueSize 786 def dpParams = coreParams.dpParams 787 788 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 789 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 790 791 def NumRedirect = backendParams.numRedirect 792 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 793 def FtqRedirectAheadNum = NumRedirect 794 def IfuRedirectNum = coreParams.IfuRedirectNum 795 def LoadPipelineWidth = coreParams.LoadPipelineWidth 796 def StorePipelineWidth = coreParams.StorePipelineWidth 797 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 798 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 799 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 800 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 801 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 802 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 803 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 804 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 805 def StoreBufferSize = coreParams.StoreBufferSize 806 def StoreBufferThreshold = coreParams.StoreBufferThreshold 807 def EnsbufferWidth = coreParams.EnsbufferWidth 808 def LoadDependencyWidth = coreParams.LoadDependencyWidth 809 def VlMergeBufferSize = coreParams.VlMergeBufferSize 810 def VsMergeBufferSize = coreParams.VsMergeBufferSize 811 def UopWritebackWidth = coreParams.UopWritebackWidth 812 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 813 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 814 def VSegmentBufferSize = coreParams.VSegmentBufferSize 815 def VFOFBufferSize = coreParams.VFOFBufferSize 816 def UncacheBufferSize = coreParams.UncacheBufferSize 817 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 818 def EnableFastForward = coreParams.EnableFastForward 819 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 820 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 821 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 822 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 823 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 824 def EnableHardwareStoreMisalign = coreParams.EnableHardwareStoreMisalign 825 def EnableHardwareLoadMisalign = coreParams.EnableHardwareLoadMisalign 826 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 827 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 828 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 829 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 830 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 831 def HasCMO = coreParams.HasCMO && p(EnableCHI) 832 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 833 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 834 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 835 def asidLen = coreParams.MMUAsidLen 836 def vmidLen = coreParams.MMUVmidLen 837 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 838 def refillBothTlb = coreParams.refillBothTlb 839 def iwpuParam = coreParams.iwpuParameters 840 def dwpuParam = coreParams.dwpuParameters 841 def itlbParams = coreParams.itlbParameters 842 def ldtlbParams = coreParams.ldtlbParameters 843 def sttlbParams = coreParams.sttlbParameters 844 def hytlbParams = coreParams.hytlbParameters 845 def pftlbParams = coreParams.pftlbParameters 846 def l2ToL1Params = coreParams.l2ToL1tlbParameters 847 def btlbParams = coreParams.btlbParameters 848 def l2tlbParams = coreParams.l2tlbParameters 849 def NumPerfCounters = coreParams.NumPerfCounters 850 851 def instBytes = if (HasCExtension) 2 else 4 852 def instOffsetBits = log2Ceil(instBytes) 853 854 def icacheParameters = coreParams.icacheParameters 855 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 856 857 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 858 // for constrained LR/SC loop 859 def LRSCCycles = 64 860 // for lr storm 861 def LRSCBackOff = 8 862 863 // cache hierarchy configurations 864 def l1BusDataWidth = 256 865 866 // load violation predict 867 def ResetTimeMax2Pow = 20 //1078576 868 def ResetTimeMin2Pow = 10 //1024 869 // wait table parameters 870 def WaitTableSize = 1024 871 def MemPredPCWidth = log2Up(WaitTableSize) 872 def LWTUse2BitCounter = true 873 // store set parameters 874 def SSITSize = WaitTableSize 875 def LFSTSize = 32 876 def SSIDWidth = log2Up(LFSTSize) 877 def LFSTWidth = 4 878 def StoreSetEnable = true // LWT will be disabled if SS is enabled 879 def LFSTEnable = true 880 881 def PCntIncrStep: Int = 6 882 def numPCntHc: Int = 12 883 def numPCntPtw: Int = 19 884 885 def numCSRPCntFrontend = 8 886 def numCSRPCntCtrl = 8 887 def numCSRPCntLsu = 8 888 def numCSRPCntHc = 5 889 def printEventCoding = true 890 def printCriticalError = false 891 def maxCommitStuck = pow(2, 21).toInt 892 893 // Vector load exception 894 def maxMergeNumPerCycle = 4 895 896 // Parameters for Sdtrig extension 897 protected def TriggerNum = 4 898 protected def TriggerChainMaxLength = 2 899 900 // Parameters for Trace extension 901 def TraceGroupNum = coreParams.traceParams.TraceGroupNum 902 def CauseWidth = XLEN 903 def TvalWidth = coreParams.traceParams.IaddrWidth 904 def PrivWidth = coreParams.traceParams.PrivWidth 905 def IaddrWidth = coreParams.traceParams.IaddrWidth 906 def ItypeWidth = coreParams.traceParams.ItypeWidth 907 def IretireWidthInPipe = log2Up(RenameWidth * 2) 908 def IretireWidthCompressed = log2Up(RenameWidth * CommitWidth * 2) 909 def IlastsizeWidth = coreParams.traceParams.IlastsizeWidth 910} 911