1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 VLEN: Int = 128, 45 HasMExtension: Boolean = true, 46 HasCExtension: Boolean = true, 47 HasDiv: Boolean = true, 48 HasICache: Boolean = true, 49 HasDCache: Boolean = true, 50 AddrBits: Int = 64, 51 VAddrBits: Int = 39, 52 HasFPU: Boolean = true, 53 HasVPU: Boolean = true, 54 HasCustomCSRCacheOp: Boolean = true, 55 FetchWidth: Int = 8, 56 AsidLength: Int = 16, 57 EnableBPU: Boolean = true, 58 EnableBPD: Boolean = true, 59 EnableRAS: Boolean = true, 60 EnableLB: Boolean = false, 61 EnableLoop: Boolean = true, 62 EnableSC: Boolean = true, 63 EnbaleTlbDebug: Boolean = false, 64 EnableJal: Boolean = false, 65 EnableFauFTB: Boolean = true, 66 UbtbGHRLength: Int = 4, 67 // HistoryLength: Int = 512, 68 EnableGHistDiff: Boolean = true, 69 UbtbSize: Int = 256, 70 FtbSize: Int = 2048, 71 RasSize: Int = 32, 72 CacheLineSize: Int = 512, 73 FtbWays: Int = 4, 74 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 75 // Sets Hist Tag 76 // Seq(( 2048, 2, 8), 77 // ( 2048, 9, 8), 78 // ( 2048, 13, 8), 79 // ( 2048, 20, 8), 80 // ( 2048, 26, 8), 81 // ( 2048, 44, 8), 82 // ( 2048, 73, 8), 83 // ( 2048, 256, 8)), 84 Seq(( 4096, 8, 8), 85 ( 4096, 13, 8), 86 ( 4096, 32, 8), 87 ( 4096, 119, 8)), 88 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 89 // Sets Hist Tag 90 Seq(( 256, 4, 9), 91 ( 256, 8, 9), 92 ( 512, 13, 9), 93 ( 512, 16, 9), 94 ( 512, 32, 9)), 95 SCNRows: Int = 512, 96 SCNTables: Int = 4, 97 SCCtrBits: Int = 6, 98 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 99 numBr: Int = 2, 100 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 101 ((resp_in: BranchPredictionResp, p: Parameters) => { 102 val ftb = Module(new FTB()(p)) 103 val ubtb =Module(new FauFTB()(p)) 104 // val bim = Module(new BIM()(p)) 105 val tage = Module(new Tage_SC()(p)) 106 val ras = Module(new RAS()(p)) 107 val ittage = Module(new ITTage()(p)) 108 val preds = Seq(ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 ubtb.io.in.bits.resp_in(0) := resp_in 117 tage.io.in.bits.resp_in(0) := ubtb.io.out 118 ftb.io.in.bits.resp_in(0) := tage.io.out 119 ittage.io.in.bits.resp_in(0) := ftb.io.out 120 ras.io.in.bits.resp_in(0) := ittage.io.out 121 122 (preds, ras.io.out) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 IntPhyRegs: Int = 192, 133 VfPhyRegs: Int = 192, 134 LoadQueueSize: Int = 80, 135 LoadQueueNWriteBanks: Int = 8, 136 StoreQueueSize: Int = 64, 137 StoreQueueNWriteBanks: Int = 8, 138 VlsQueueSize: Int = 8, 139 RobSize: Int = 256, 140 dpParams: DispatchParameters = DispatchParameters( 141 IntDqSize = 16, 142 FpDqSize = 16, 143 LsDqSize = 16, 144 IntDqDeqWidth = 4, 145 FpDqDeqWidth = 4, 146 LsDqDeqWidth = 4 147 ), 148 exuParameters: ExuParameters = ExuParameters( 149 JmpCnt = 1, 150 AluCnt = 4, 151 MulCnt = 0, 152 MduCnt = 2, 153 FmacCnt = 4, 154 FmiscCnt = 2, 155 FmiscDivSqrtCnt = 0, 156 LduCnt = 2, 157 StuCnt = 2 158 ), 159 LoadPipelineWidth: Int = 2, 160 StorePipelineWidth: Int = 2, 161 VecMemSrcInWidth: Int = 2, 162 VecMemInstWbWidth: Int = 1, 163 VecMemDispatchWidth: Int = 1, 164 StoreBufferSize: Int = 16, 165 StoreBufferThreshold: Int = 7, 166 EnsbufferWidth: Int = 2, 167 UncacheBufferSize: Int = 4, 168 EnableLoadToLoadForward: Boolean = true, 169 EnableFastForward: Boolean = false, 170 EnableLdVioCheckAfterReset: Boolean = true, 171 EnableSoftPrefetchAfterReset: Boolean = true, 172 EnableCacheErrorAfterReset: Boolean = true, 173 EnableDCacheWPU: Boolean = false, 174 EnableAccurateLoadError: Boolean = true, 175 EnableUncacheWriteOutstanding: Boolean = true, 176 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 177 ReSelectLen: Int = 6, // load replay queue replay select counter len 178 itlbParameters: TLBParameters = TLBParameters( 179 name = "itlb", 180 fetchi = true, 181 useDmode = false, 182 normalNWays = 32, 183 normalReplacer = Some("plru"), 184 superNWays = 4, 185 superReplacer = Some("plru") 186 ), 187 ldtlbParameters: TLBParameters = TLBParameters( 188 name = "ldtlb", 189 normalNSets = 64, 190 normalNWays = 1, 191 normalAssociative = "sa", 192 normalReplacer = Some("setplru"), 193 superNWays = 16, 194 normalAsVictim = true, 195 outReplace = false, 196 partialStaticPMP = true, 197 outsideRecvFlush = true, 198 saveLevel = true 199 ), 200 sttlbParameters: TLBParameters = TLBParameters( 201 name = "sttlb", 202 normalNSets = 64, 203 normalNWays = 1, 204 normalAssociative = "sa", 205 normalReplacer = Some("setplru"), 206 superNWays = 16, 207 normalAsVictim = true, 208 outReplace = false, 209 partialStaticPMP = true, 210 outsideRecvFlush = true, 211 saveLevel = true 212 ), 213 refillBothTlb: Boolean = false, 214 btlbParameters: TLBParameters = TLBParameters( 215 name = "btlb", 216 normalNSets = 1, 217 normalNWays = 64, 218 superNWays = 4, 219 ), 220 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 221 NumPerfCounters: Int = 16, 222 icacheParameters: ICacheParameters = ICacheParameters( 223 tagECC = Some("parity"), 224 dataECC = Some("parity"), 225 replacer = Some("setplru"), 226 nMissEntries = 2, 227 nProbeEntries = 2, 228 nPrefetchEntries = 2, 229 hasPrefetch = true, 230 ), 231 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 232 tagECC = Some("secded"), 233 dataECC = Some("secded"), 234 replacer = Some("setplru"), 235 nMissEntries = 16, 236 nProbeEntries = 8, 237 nReleaseEntries = 18 238 )), 239 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 240 name = "l2", 241 level = 2, 242 ways = 8, 243 sets = 1024, // default 512KB L2 244 prefetch = Some(huancun.prefetch.BOPParameters()) 245 )), 246 L2NBanks: Int = 1, 247 usePTWRepeater: Boolean = false, 248 softPTW: Boolean = false, // dpi-c debug only 249 softPTWDelay: Int = 1 250){ 251 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 252 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 253 254 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 255 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 256 257 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 258 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 259 260 val fpExuConfigs = 261 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 262 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 263 264 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 265} 266 267case object DebugOptionsKey extends Field[DebugOptions] 268 269case class DebugOptions 270( 271 FPGAPlatform: Boolean = false, 272 EnableDifftest: Boolean = false, 273 AlwaysBasicDiff: Boolean = true, 274 EnableDebug: Boolean = false, 275 EnablePerfDebug: Boolean = true, 276 UseDRAMSim: Boolean = false, 277 EnableTopDown: Boolean = false 278) 279 280trait HasXSParameter { 281 282 implicit val p: Parameters 283 284 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 285 286 val coreParams = p(XSCoreParamsKey) 287 val env = p(DebugOptionsKey) 288 289 val XLEN = coreParams.XLEN 290 val VLEN = coreParams.VLEN 291 val minFLen = 32 292 val fLen = 64 293 def xLen = XLEN 294 295 val HasMExtension = coreParams.HasMExtension 296 val HasCExtension = coreParams.HasCExtension 297 val HasDiv = coreParams.HasDiv 298 val HasIcache = coreParams.HasICache 299 val HasDcache = coreParams.HasDCache 300 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 301 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 302 val AsidLength = coreParams.AsidLength 303 val ReSelectLen = coreParams.ReSelectLen 304 val AddrBytes = AddrBits / 8 // unused 305 val DataBits = XLEN 306 val DataBytes = DataBits / 8 307 val HasFPU = coreParams.HasFPU 308 val HasVPU = coreParams.HasVPU 309 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 310 val FetchWidth = coreParams.FetchWidth 311 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 312 val EnableBPU = coreParams.EnableBPU 313 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 314 val EnableRAS = coreParams.EnableRAS 315 val EnableLB = coreParams.EnableLB 316 val EnableLoop = coreParams.EnableLoop 317 val EnableSC = coreParams.EnableSC 318 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 319 val HistoryLength = coreParams.HistoryLength 320 val EnableGHistDiff = coreParams.EnableGHistDiff 321 val UbtbGHRLength = coreParams.UbtbGHRLength 322 val UbtbSize = coreParams.UbtbSize 323 val EnableFauFTB = coreParams.EnableFauFTB 324 val FtbSize = coreParams.FtbSize 325 val FtbWays = coreParams.FtbWays 326 val RasSize = coreParams.RasSize 327 328 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 329 coreParams.branchPredictor(resp_in, p) 330 } 331 val numBr = coreParams.numBr 332 val TageTableInfos = coreParams.TageTableInfos 333 val TageBanks = coreParams.numBr 334 val SCNRows = coreParams.SCNRows 335 val SCCtrBits = coreParams.SCCtrBits 336 val SCHistLens = coreParams.SCHistLens 337 val SCNTables = coreParams.SCNTables 338 339 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 340 case ((n, cb), h) => (n, cb, h) 341 } 342 val ITTageTableInfos = coreParams.ITTageTableInfos 343 type FoldedHistoryInfo = Tuple2[Int, Int] 344 val foldedGHistInfos = 345 (TageTableInfos.map{ case (nRows, h, t) => 346 if (h > 0) 347 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 348 else 349 Set[FoldedHistoryInfo]() 350 }.reduce(_++_).toSet ++ 351 SCTableInfos.map{ case (nRows, _, h) => 352 if (h > 0) 353 Set((h, min(log2Ceil(nRows/TageBanks), h))) 354 else 355 Set[FoldedHistoryInfo]() 356 }.reduce(_++_).toSet ++ 357 ITTageTableInfos.map{ case (nRows, h, t) => 358 if (h > 0) 359 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 360 else 361 Set[FoldedHistoryInfo]() 362 }.reduce(_++_) ++ 363 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 364 ).toList 365 366 367 368 val CacheLineSize = coreParams.CacheLineSize 369 val CacheLineHalfWord = CacheLineSize / 16 370 val ExtHistoryLength = HistoryLength + 64 371 val IBufSize = coreParams.IBufSize 372 val DecodeWidth = coreParams.DecodeWidth 373 val RenameWidth = coreParams.RenameWidth 374 val CommitWidth = coreParams.CommitWidth 375 val FtqSize = coreParams.FtqSize 376 val IssQueSize = coreParams.IssQueSize 377 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 378 val NRPhyRegs = coreParams.NRPhyRegs 379 val PhyRegIdxWidth = log2Up(NRPhyRegs) 380 val IntPhyRegs = coreParams.IntPhyRegs 381 val VfPhyRegs = coreParams.VfPhyRegs 382 val IntPregIdxWidth = log2Up(IntPhyRegs) 383 val VfPregIdxWidth = log2Up(VfPhyRegs) 384 val RobSize = coreParams.RobSize 385 val IntRefCounterWidth = log2Ceil(RobSize) 386 val LoadQueueSize = coreParams.LoadQueueSize 387 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 388 val StoreQueueSize = coreParams.StoreQueueSize 389 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 390 val VlsQueueSize = coreParams.VlsQueueSize 391 val dpParams = coreParams.dpParams 392 val exuParameters = coreParams.exuParameters 393 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 394 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 395 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 396 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 397 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 398 val LoadPipelineWidth = coreParams.LoadPipelineWidth 399 val StorePipelineWidth = coreParams.StorePipelineWidth 400 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 401 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 402 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 403 val StoreBufferSize = coreParams.StoreBufferSize 404 val StoreBufferThreshold = coreParams.StoreBufferThreshold 405 val EnsbufferWidth = coreParams.EnsbufferWidth 406 val UncacheBufferSize = coreParams.UncacheBufferSize 407 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 408 val EnableFastForward = coreParams.EnableFastForward 409 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 410 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 411 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 412 val EnableDCacheWPU = coreParams.EnableDCacheWPU 413 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 414 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 415 val asidLen = coreParams.MMUAsidLen 416 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 417 val refillBothTlb = coreParams.refillBothTlb 418 val itlbParams = coreParams.itlbParameters 419 val ldtlbParams = coreParams.ldtlbParameters 420 val sttlbParams = coreParams.sttlbParameters 421 val btlbParams = coreParams.btlbParameters 422 val l2tlbParams = coreParams.l2tlbParameters 423 val NumPerfCounters = coreParams.NumPerfCounters 424 425 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 426 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 427 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 428 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 429 430 val instBytes = if (HasCExtension) 2 else 4 431 val instOffsetBits = log2Ceil(instBytes) 432 433 val icacheParameters = coreParams.icacheParameters 434 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 435 436 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 437 // for constrained LR/SC loop 438 val LRSCCycles = 64 439 // for lr storm 440 val LRSCBackOff = 8 441 442 // cache hierarchy configurations 443 val l1BusDataWidth = 256 444 445 // load violation predict 446 val ResetTimeMax2Pow = 20 //1078576 447 val ResetTimeMin2Pow = 10 //1024 448 // wait table parameters 449 val WaitTableSize = 1024 450 val MemPredPCWidth = log2Up(WaitTableSize) 451 val LWTUse2BitCounter = true 452 // store set parameters 453 val SSITSize = WaitTableSize 454 val LFSTSize = 32 455 val SSIDWidth = log2Up(LFSTSize) 456 val LFSTWidth = 4 457 val StoreSetEnable = true // LWT will be disabled if SS is enabled 458 459 val loadExuConfigs = coreParams.loadExuConfigs 460 val storeExuConfigs = coreParams.storeExuConfigs 461 462 val intExuConfigs = coreParams.intExuConfigs 463 464 val fpExuConfigs = coreParams.fpExuConfigs 465 466 val exuConfigs = coreParams.exuConfigs 467 468 val PCntIncrStep: Int = 6 469 val numPCntHc: Int = 25 470 val numPCntPtw: Int = 19 471 472 val numCSRPCntFrontend = 8 473 val numCSRPCntCtrl = 8 474 val numCSRPCntLsu = 8 475 val numCSRPCntHc = 5 476} 477