1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableJal: Boolean = false, 82 EnableFauFTB: Boolean = true, 83 UbtbGHRLength: Int = 4, 84 // HistoryLength: Int = 512, 85 EnableGHistDiff: Boolean = true, 86 EnableCommitGHistDiff: Boolean = true, 87 UbtbSize: Int = 256, 88 FtbSize: Int = 2048, 89 RasSize: Int = 32, 90 CacheLineSize: Int = 512, 91 FtbWays: Int = 4, 92 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 93 // Sets Hist Tag 94 // Seq(( 2048, 2, 8), 95 // ( 2048, 9, 8), 96 // ( 2048, 13, 8), 97 // ( 2048, 20, 8), 98 // ( 2048, 26, 8), 99 // ( 2048, 44, 8), 100 // ( 2048, 73, 8), 101 // ( 2048, 256, 8)), 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 119 ((resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val ubtb =Module(new FauFTB()(p)) 122 // val bim = Module(new BIM()(p)) 123 val tage = Module(new Tage_SC()(p)) 124 val ras = Module(new RAS()(p)) 125 val ittage = Module(new ITTage()(p)) 126 val preds = Seq(ubtb, tage, ftb, ittage, ras) 127 preds.map(_.io := DontCare) 128 129 // ubtb.io.resp_in(0) := resp_in 130 // bim.io.resp_in(0) := ubtb.io.resp 131 // btb.io.resp_in(0) := bim.io.resp 132 // tage.io.resp_in(0) := btb.io.resp 133 // loop.io.resp_in(0) := tage.io.resp 134 ubtb.io.in.bits.resp_in(0) := resp_in 135 tage.io.in.bits.resp_in(0) := ubtb.io.out 136 ftb.io.in.bits.resp_in(0) := tage.io.out 137 ittage.io.in.bits.resp_in(0) := ftb.io.out 138 ras.io.in.bits.resp_in(0) := ittage.io.out 139 140 (preds, ras.io.out) 141 }), 142 IBufSize: Int = 48, 143 DecodeWidth: Int = 6, 144 RenameWidth: Int = 6, 145 CommitWidth: Int = 6, 146 MaxUopSize: Int = 65, 147 EnableRenameSnapshot: Boolean = true, 148 RenameSnapshotNum: Int = 4, 149 FtqSize: Int = 64, 150 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 151 IntLogicRegs: Int = 32, 152 FpLogicRegs: Int = 33, 153 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 154 VCONFIG_IDX: Int = 32, 155 NRPhyRegs: Int = 192, 156 VirtualLoadQueueSize: Int = 80, 157 LoadQueueRARSize: Int = 80, 158 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 159 RollbackGroupSize: Int = 8, 160 LoadQueueReplaySize: Int = 72, 161 LoadUncacheBufferSize: Int = 20, 162 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 163 StoreQueueSize: Int = 64, 164 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 165 StoreQueueForwardWithMask: Boolean = true, 166 VlsQueueSize: Int = 8, 167 RobSize: Int = 256, 168 RabSize: Int = 256, 169 IssueQueueSize: Int = 32, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 16, 174 IntDqDeqWidth = 6, 175 FpDqDeqWidth = 6, 176 LsDqDeqWidth = 6, 177 ), 178 intPreg: PregParams = IntPregParams( 179 numEntries = 192, 180 numRead = None, 181 numWrite = None, 182 ), 183 vfPreg: VfPregParams = VfPregParams( 184 numEntries = 192, 185 numRead = None, 186 numWrite = None, 187 ), 188 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 189 LoadPipelineWidth: Int = 2, 190 StorePipelineWidth: Int = 2, 191 VecMemSrcInWidth: Int = 2, 192 VecMemInstWbWidth: Int = 1, 193 VecMemDispatchWidth: Int = 1, 194 StoreBufferSize: Int = 16, 195 StoreBufferThreshold: Int = 7, 196 EnsbufferWidth: Int = 2, 197 UncacheBufferSize: Int = 4, 198 EnableLoadToLoadForward: Boolean = true, 199 EnableFastForward: Boolean = true, 200 EnableLdVioCheckAfterReset: Boolean = true, 201 EnableSoftPrefetchAfterReset: Boolean = true, 202 EnableCacheErrorAfterReset: Boolean = true, 203 EnableAccurateLoadError: Boolean = true, 204 EnableUncacheWriteOutstanding: Boolean = false, 205 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 206 ReSelectLen: Int = 7, // load replay queue replay select counter len 207 iwpuParameters: WPUParameters = WPUParameters( 208 enWPU = false, 209 algoName = "mmru", 210 isICache = true, 211 ), 212 dwpuParameters: WPUParameters = WPUParameters( 213 enWPU = false, 214 algoName = "mmru", 215 enCfPred = false, 216 isICache = false, 217 ), 218 itlbParameters: TLBParameters = TLBParameters( 219 name = "itlb", 220 fetchi = true, 221 useDmode = false, 222 normalNWays = 32, 223 normalReplacer = Some("plru"), 224 superNWays = 4, 225 superReplacer = Some("plru") 226 ), 227 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 228 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 229 ldtlbParameters: TLBParameters = TLBParameters( 230 name = "ldtlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 sttlbParameters: TLBParameters = TLBParameters( 243 name = "sttlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 pftlbParameters: TLBParameters = TLBParameters( 256 name = "pftlb", 257 normalNSets = 64, 258 normalNWays = 1, 259 normalAssociative = "sa", 260 normalReplacer = Some("setplru"), 261 superNWays = 16, 262 normalAsVictim = true, 263 outReplace = false, 264 partialStaticPMP = true, 265 outsideRecvFlush = true, 266 saveLevel = true 267 ), 268 refillBothTlb: Boolean = false, 269 btlbParameters: TLBParameters = TLBParameters( 270 name = "btlb", 271 normalNSets = 1, 272 normalNWays = 64, 273 superNWays = 4, 274 ), 275 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 276 NumPerfCounters: Int = 16, 277 icacheParameters: ICacheParameters = ICacheParameters( 278 tagECC = Some("parity"), 279 dataECC = Some("parity"), 280 replacer = Some("setplru"), 281 nMissEntries = 2, 282 nProbeEntries = 2, 283 nPrefetchEntries = 12, 284 nPrefBufferEntries = 64, 285 hasPrefetch = true, 286 ), 287 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 288 tagECC = Some("secded"), 289 dataECC = Some("secded"), 290 replacer = Some("setplru"), 291 nMissEntries = 16, 292 nProbeEntries = 8, 293 nReleaseEntries = 18 294 )), 295 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 296 name = "l2", 297 ways = 8, 298 sets = 1024, // default 512KB L2 299 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 300 )), 301 L2NBanks: Int = 1, 302 usePTWRepeater: Boolean = false, 303 softTLB: Boolean = false, // dpi-c l1tlb debug only 304 softPTW: Boolean = false, // dpi-c l2tlb debug only 305 softPTWDelay: Int = 1 306){ 307 def vlWidth = log2Up(VLEN) + 1 308 309 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 310 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 311 312 val intSchdParams = { 313 implicit val schdType: SchedulerType = IntScheduler() 314 SchdBlockParams(Seq( 315 IssueBlockParams(Seq( 316 ExeUnitParams("ALU0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 317 ExeUnitParams("ALU1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 318 ), numEntries = IssueQueueSize, numEnq = 2), 319 IssueBlockParams(Seq( 320 ExeUnitParams("MUL0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 321 ExeUnitParams("MUL1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 322 ), numEntries = IssueQueueSize, numEnq = 2), 323 IssueBlockParams(Seq( 324 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 325 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 326 ), numEntries = IssueQueueSize, numEnq = 2), 327 IssueBlockParams(Seq( 328 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 329 ), numEntries = IssueQueueSize, numEnq = 2), 330 IssueBlockParams(Seq( 331 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 332 ), numEntries = IssueQueueSize, numEnq = 2), 333 ), 334 numPregs = intPreg.numEntries, 335 numDeqOutside = 0, 336 schdType = schdType, 337 rfDataWidth = intPreg.dataCfg.dataWidth, 338 numUopIn = dpParams.IntDqDeqWidth, 339 ) 340 } 341 val vfSchdParams = { 342 implicit val schdType: SchedulerType = VfScheduler() 343 SchdBlockParams(Seq( 344 IssueBlockParams(Seq( 345 ExeUnitParams("FEX0", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(12, 0)), Seq(VfRD(13, 0)))), 346 ), numEntries = IssueQueueSize, numEnq = 2), 347 IssueBlockParams(Seq( 348 ExeUnitParams("VEX0", Seq(VialuCfg, VimacCfg, VppuCfg, VipuCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 349 ), numEntries = IssueQueueSize, numEnq = 2), 350 IssueBlockParams(Seq( 351 ExeUnitParams("VEX1", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 2, 0), IntWB(port = 8, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 352 ExeUnitParams("VEX2", Seq(VfaluCfg, VfmaCfg), Seq(VfWB(port = 3, 0), IntWB(port = 9, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 353 ), numEntries = IssueQueueSize, numEnq = 2), 354 IssueBlockParams(Seq( 355 ExeUnitParams("VEX3", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 356 ), numEntries = IssueQueueSize, numEnq = 2), 357 ), 358 numPregs = vfPreg.numEntries, 359 numDeqOutside = 0, 360 schdType = schdType, 361 rfDataWidth = vfPreg.dataCfg.dataWidth, 362 numUopIn = dpParams.FpDqDeqWidth, 363 ) 364 } 365 366 val memSchdParams = { 367 implicit val schdType: SchedulerType = MemScheduler() 368 val rfDataWidth = 64 369 370 SchdBlockParams(Seq( 371 IssueBlockParams(Seq( 372 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 373 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 374 ), numEntries = IssueQueueSize, numEnq = 2), 375 IssueBlockParams(Seq( 376 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(10, 0)), Seq(Seq(IntRD(12, 0)))), 377 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(11, 0)), Seq(Seq(IntRD(13, 0)))), 378 ), numEntries = IssueQueueSize, numEnq = 2), 379 IssueBlockParams(Seq( 380 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 381 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 382 ), numEntries = IssueQueueSize, numEnq = 2), 383 IssueBlockParams(Seq( 384 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 385 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 386 ), numEntries = IssueQueueSize, numEnq = 2), 387 ), 388 numPregs = intPreg.numEntries max vfPreg.numEntries, 389 numDeqOutside = 0, 390 schdType = schdType, 391 rfDataWidth = rfDataWidth, 392 numUopIn = dpParams.LsDqDeqWidth, 393 ) 394 } 395 396 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 397 398 def iqWakeUpParams = { 399 Seq( 400 WakeUpConfig( 401 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "LDU0", "LDU1") -> 402 Seq("ALU0", "ALU1", "MUL0", "MUL1", "BJU0", "BJU1", "LDU0", "LDU1", "STA0", "STA1", "STD0", "STD1") 403 ), 404 WakeUpConfig(Seq("IMISC0") -> Seq("FEX0")), 405 ).flatten 406 } 407 408 def backendParams: BackendParams = backend.BackendParams( 409 Map( 410 IntScheduler() -> intSchdParams, 411 VfScheduler() -> vfSchdParams, 412 MemScheduler() -> memSchdParams, 413 ), 414 Seq( 415 intPreg, 416 vfPreg, 417 ), 418 iqWakeUpParams, 419 ) 420} 421 422case object DebugOptionsKey extends Field[DebugOptions] 423 424case class DebugOptions 425( 426 FPGAPlatform: Boolean = false, 427 EnableDifftest: Boolean = false, 428 AlwaysBasicDiff: Boolean = true, 429 EnableDebug: Boolean = false, 430 EnablePerfDebug: Boolean = true, 431 UseDRAMSim: Boolean = false, 432 EnableConstantin: Boolean = false, 433 EnableChiselDB: Boolean = false, 434 AlwaysBasicDB: Boolean = true, 435 EnableTopDown: Boolean = false, 436) 437 438trait HasXSParameter { 439 440 implicit val p: Parameters 441 442 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 443 444 val coreParams = p(XSCoreParamsKey) 445 val env = p(DebugOptionsKey) 446 447 val XLEN = coreParams.XLEN 448 val VLEN = coreParams.VLEN 449 val ELEN = coreParams.ELEN 450 val minFLen = 32 451 val fLen = 64 452 def xLen = XLEN 453 454 val HasMExtension = coreParams.HasMExtension 455 val HasCExtension = coreParams.HasCExtension 456 val HasDiv = coreParams.HasDiv 457 val HasIcache = coreParams.HasICache 458 val HasDcache = coreParams.HasDCache 459 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 460 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 461 val AsidLength = coreParams.AsidLength 462 val ReSelectLen = coreParams.ReSelectLen 463 val AddrBytes = AddrBits / 8 // unused 464 val DataBits = XLEN 465 val DataBytes = DataBits / 8 466 val VDataBytes = VLEN / 8 467 val HasFPU = coreParams.HasFPU 468 val HasVPU = coreParams.HasVPU 469 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 470 val FetchWidth = coreParams.FetchWidth 471 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 472 val EnableBPU = coreParams.EnableBPU 473 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 474 val EnableRAS = coreParams.EnableRAS 475 val EnableLB = coreParams.EnableLB 476 val EnableLoop = coreParams.EnableLoop 477 val EnableSC = coreParams.EnableSC 478 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 479 val HistoryLength = coreParams.HistoryLength 480 val EnableGHistDiff = coreParams.EnableGHistDiff 481 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 482 val UbtbGHRLength = coreParams.UbtbGHRLength 483 val UbtbSize = coreParams.UbtbSize 484 val EnableFauFTB = coreParams.EnableFauFTB 485 val FtbSize = coreParams.FtbSize 486 val FtbWays = coreParams.FtbWays 487 val RasSize = coreParams.RasSize 488 489 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 490 coreParams.branchPredictor(resp_in, p) 491 } 492 val numBr = coreParams.numBr 493 val TageTableInfos = coreParams.TageTableInfos 494 val TageBanks = coreParams.numBr 495 val SCNRows = coreParams.SCNRows 496 val SCCtrBits = coreParams.SCCtrBits 497 val SCHistLens = coreParams.SCHistLens 498 val SCNTables = coreParams.SCNTables 499 500 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 501 case ((n, cb), h) => (n, cb, h) 502 } 503 val ITTageTableInfos = coreParams.ITTageTableInfos 504 type FoldedHistoryInfo = Tuple2[Int, Int] 505 val foldedGHistInfos = 506 (TageTableInfos.map{ case (nRows, h, t) => 507 if (h > 0) 508 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 509 else 510 Set[FoldedHistoryInfo]() 511 }.reduce(_++_).toSet ++ 512 SCTableInfos.map{ case (nRows, _, h) => 513 if (h > 0) 514 Set((h, min(log2Ceil(nRows/TageBanks), h))) 515 else 516 Set[FoldedHistoryInfo]() 517 }.reduce(_++_).toSet ++ 518 ITTageTableInfos.map{ case (nRows, h, t) => 519 if (h > 0) 520 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 521 else 522 Set[FoldedHistoryInfo]() 523 }.reduce(_++_) ++ 524 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 525 ).toList 526 527 528 529 val CacheLineSize = coreParams.CacheLineSize 530 val CacheLineHalfWord = CacheLineSize / 16 531 val ExtHistoryLength = HistoryLength + 64 532 val IBufSize = coreParams.IBufSize 533 val DecodeWidth = coreParams.DecodeWidth 534 val RenameWidth = coreParams.RenameWidth 535 val CommitWidth = coreParams.CommitWidth 536 val MaxUopSize = coreParams.MaxUopSize 537 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 538 val RenameSnapshotNum = coreParams.RenameSnapshotNum 539 val FtqSize = coreParams.FtqSize 540 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 541 val IntLogicRegs = coreParams.IntLogicRegs 542 val FpLogicRegs = coreParams.FpLogicRegs 543 val VecLogicRegs = coreParams.VecLogicRegs 544 val VCONFIG_IDX = coreParams.VCONFIG_IDX 545 val IntPhyRegs = coreParams.intPreg.numEntries 546 val VfPhyRegs = coreParams.vfPreg.numEntries 547 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 548 val RobSize = coreParams.RobSize 549 val RabSize = coreParams.RabSize 550 val IntRefCounterWidth = log2Ceil(RobSize) 551 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 552 val LoadQueueRARSize = coreParams.LoadQueueRARSize 553 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 554 val RollbackGroupSize = coreParams.RollbackGroupSize 555 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 556 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 557 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 558 val StoreQueueSize = coreParams.StoreQueueSize 559 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 560 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 561 val VlsQueueSize = coreParams.VlsQueueSize 562 val dpParams = coreParams.dpParams 563 564 def backendParams: BackendParams = coreParams.backendParams 565 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 566 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 567 val LoadPipelineWidth = coreParams.LoadPipelineWidth 568 val StorePipelineWidth = coreParams.StorePipelineWidth 569 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 570 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 571 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 572 val StoreBufferSize = coreParams.StoreBufferSize 573 val StoreBufferThreshold = coreParams.StoreBufferThreshold 574 val EnsbufferWidth = coreParams.EnsbufferWidth 575 val UncacheBufferSize = coreParams.UncacheBufferSize 576 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 577 val EnableFastForward = coreParams.EnableFastForward 578 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 579 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 580 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 581 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 582 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 583 val asidLen = coreParams.MMUAsidLen 584 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 585 val refillBothTlb = coreParams.refillBothTlb 586 val iwpuParam = coreParams.iwpuParameters 587 val dwpuParam = coreParams.dwpuParameters 588 val itlbParams = coreParams.itlbParameters 589 val ldtlbParams = coreParams.ldtlbParameters 590 val sttlbParams = coreParams.sttlbParameters 591 val pftlbParams = coreParams.pftlbParameters 592 val btlbParams = coreParams.btlbParameters 593 val l2tlbParams = coreParams.l2tlbParameters 594 val NumPerfCounters = coreParams.NumPerfCounters 595 596 val instBytes = if (HasCExtension) 2 else 4 597 val instOffsetBits = log2Ceil(instBytes) 598 599 val icacheParameters = coreParams.icacheParameters 600 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 601 602 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 603 // for constrained LR/SC loop 604 val LRSCCycles = 64 605 // for lr storm 606 val LRSCBackOff = 8 607 608 // cache hierarchy configurations 609 val l1BusDataWidth = 256 610 611 // load violation predict 612 val ResetTimeMax2Pow = 20 //1078576 613 val ResetTimeMin2Pow = 10 //1024 614 // wait table parameters 615 val WaitTableSize = 1024 616 val MemPredPCWidth = log2Up(WaitTableSize) 617 val LWTUse2BitCounter = true 618 // store set parameters 619 val SSITSize = WaitTableSize 620 val LFSTSize = 32 621 val SSIDWidth = log2Up(LFSTSize) 622 val LFSTWidth = 4 623 val StoreSetEnable = true // LWT will be disabled if SS is enabled 624 val LFSTEnable = false 625 626 val PCntIncrStep: Int = 6 627 val numPCntHc: Int = 25 628 val numPCntPtw: Int = 19 629 630 val numCSRPCntFrontend = 8 631 val numCSRPCntCtrl = 8 632 val numCSRPCntLsu = 8 633 val numCSRPCntHc = 5 634} 635