1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler} 30import xiangshan.backend.regfile._ 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39import freechips.rocketchip.diplomacy.AddressSet 40import freechips.rocketchip.tile.MaxHartIdBits 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.{max, min} 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HSXLEN: Int = 64, 63 HasMExtension: Boolean = true, 64 HasCExtension: Boolean = true, 65 HasHExtension: Boolean = true, 66 HasDiv: Boolean = true, 67 HasICache: Boolean = true, 68 HasDCache: Boolean = true, 69 AddrBits: Int = 64, 70 VAddrBits: Int = 39, 71 GPAddrBits: Int = 41, 72 HasFPU: Boolean = true, 73 HasVPU: Boolean = true, 74 HasCustomCSRCacheOp: Boolean = true, 75 FetchWidth: Int = 8, 76 AsidLength: Int = 16, 77 VmidLength: Int = 14, 78 EnableBPU: Boolean = true, 79 EnableBPD: Boolean = true, 80 EnableRAS: Boolean = true, 81 EnableLB: Boolean = false, 82 EnableLoop: Boolean = true, 83 EnableSC: Boolean = true, 84 EnbaleTlbDebug: Boolean = false, 85 EnableClockGate: Boolean = true, 86 EnableJal: Boolean = false, 87 EnableFauFTB: Boolean = true, 88 UbtbGHRLength: Int = 4, 89 // HistoryLength: Int = 512, 90 EnableGHistDiff: Boolean = true, 91 EnableCommitGHistDiff: Boolean = true, 92 UbtbSize: Int = 256, 93 FtbSize: Int = 2048, 94 RasSize: Int = 16, 95 RasSpecSize: Int = 32, 96 RasCtrSize: Int = 3, 97 CacheLineSize: Int = 512, 98 FtbWays: Int = 4, 99 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 100 // Sets Hist Tag 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 118 (resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val uftb = Module(new FauFTB()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(uftb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out 128 ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out 129 130 uftb.io.in.bits.resp_in(0) := resp_in 131 tage.io.in.bits.resp_in(0) := uftb.io.out 132 ftb.io.in.bits.resp_in(0) := tage.io.out 133 ittage.io.in.bits.resp_in(0) := ftb.io.out 134 ras.io.in.bits.resp_in(0) := ittage.io.out 135 136 (preds, ras.io.out) 137 }, 138 ICacheForceMetaECCError: Boolean = false, 139 ICacheForceDataECCError: Boolean = false, 140 IBufSize: Int = 48, 141 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 8, 145 RobCommitWidth: Int = 8, 146 RabCommitWidth: Int = 6, 147 MaxUopSize: Int = 65, 148 EnableRenameSnapshot: Boolean = true, 149 RenameSnapshotNum: Int = 4, 150 FtqSize: Int = 64, 151 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 152 IntLogicRegs: Int = 32, 153 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 154 VecLogicRegs: Int = 32 + 15, // 15: tmp 155 V0LogicRegs: Int = 1, // V0 156 VlLogicRegs: Int = 1, // Vl 157 V0_IDX: Int = 0, 158 Vl_IDX: Int = 0, 159 NRPhyRegs: Int = 192, 160 VirtualLoadQueueSize: Int = 72, 161 LoadQueueRARSize: Int = 72, 162 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 163 RollbackGroupSize: Int = 8, 164 LoadQueueReplaySize: Int = 72, 165 LoadUncacheBufferSize: Int = 20, 166 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 167 StoreQueueSize: Int = 64, 168 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 169 StoreQueueForwardWithMask: Boolean = true, 170 VlsQueueSize: Int = 8, 171 RobSize: Int = 160, 172 RabSize: Int = 256, 173 VTypeBufferSize: Int = 64, // used to reorder vtype 174 IssueQueueSize: Int = 24, 175 IssueQueueCompEntrySize: Int = 16, 176 dpParams: DispatchParameters = DispatchParameters( 177 IntDqSize = 16, 178 FpDqSize = 16, 179 LsDqSize = 18, 180 IntDqDeqWidth = 8, 181 FpDqDeqWidth = 6, 182 VecDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 fpPreg: PregParams = FpPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 vfPreg: VfPregParams = VfPregParams( 196 numEntries = 128, 197 numRead = None, 198 numWrite = None, 199 ), 200 v0Preg: V0PregParams = V0PregParams( 201 numEntries = 22, 202 numRead = None, 203 numWrite = None, 204 ), 205 vlPreg: VlPregParams = VlPregParams( 206 numEntries = 32, 207 numRead = None, 208 numWrite = None, 209 ), 210 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 211 IfuRedirectNum: Int = 1, 212 LoadPipelineWidth: Int = 3, 213 StorePipelineWidth: Int = 2, 214 VecLoadPipelineWidth: Int = 2, 215 VecStorePipelineWidth: Int = 2, 216 VecMemSrcInWidth: Int = 2, 217 VecMemInstWbWidth: Int = 1, 218 VecMemDispatchWidth: Int = 1, 219 VecMemDispatchMaxNumber: Int = 16, 220 VecMemUnitStrideMaxFlowNum: Int = 2, 221 VecMemLSQEnqIteratorNumberSeq: Seq[Int] = Seq(16, 2, 2, 2, 2, 2), 222 StoreBufferSize: Int = 16, 223 StoreBufferThreshold: Int = 7, 224 EnsbufferWidth: Int = 2, 225 LoadDependencyWidth: Int = 2, 226 // ============ VLSU ============ 227 VlMergeBufferSize: Int = 16, 228 VsMergeBufferSize: Int = 16, 229 UopWritebackWidth: Int = 2, 230 VLUopWritebackWidth: Int = 2, 231 VSUopWritebackWidth: Int = 1, 232 VSegmentBufferSize: Int = 8, 233 // ============================== 234 UncacheBufferSize: Int = 4, 235 EnableLoadToLoadForward: Boolean = false, 236 EnableFastForward: Boolean = true, 237 EnableLdVioCheckAfterReset: Boolean = true, 238 EnableSoftPrefetchAfterReset: Boolean = true, 239 EnableCacheErrorAfterReset: Boolean = true, 240 EnableAccurateLoadError: Boolean = false, 241 EnableUncacheWriteOutstanding: Boolean = false, 242 EnableStorePrefetchAtIssue: Boolean = false, 243 EnableStorePrefetchAtCommit: Boolean = false, 244 EnableAtCommitMissTrigger: Boolean = true, 245 EnableStorePrefetchSMS: Boolean = false, 246 EnableStorePrefetchSPB: Boolean = false, 247 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 248 MMUVmidLen: Int = 14, 249 ReSelectLen: Int = 7, // load replay queue replay select counter len 250 iwpuParameters: WPUParameters = WPUParameters( 251 enWPU = false, 252 algoName = "mmru", 253 isICache = true, 254 ), 255 dwpuParameters: WPUParameters = WPUParameters( 256 enWPU = false, 257 algoName = "mmru", 258 enCfPred = false, 259 isICache = false, 260 ), 261 itlbParameters: TLBParameters = TLBParameters( 262 name = "itlb", 263 fetchi = true, 264 useDmode = false, 265 NWays = 48, 266 ), 267 itlbPortNum: Int = ICacheParameters().PortNumber + 1, 268 ipmpPortNum: Int = 2 * ICacheParameters().PortNumber + 1, 269 ldtlbParameters: TLBParameters = TLBParameters( 270 name = "ldtlb", 271 NWays = 48, 272 outReplace = false, 273 partialStaticPMP = true, 274 outsideRecvFlush = true, 275 saveLevel = true, 276 lgMaxSize = 4 277 ), 278 sttlbParameters: TLBParameters = TLBParameters( 279 name = "sttlb", 280 NWays = 48, 281 outReplace = false, 282 partialStaticPMP = true, 283 outsideRecvFlush = true, 284 saveLevel = true, 285 lgMaxSize = 4 286 ), 287 hytlbParameters: TLBParameters = TLBParameters( 288 name = "hytlb", 289 NWays = 48, 290 outReplace = false, 291 partialStaticPMP = true, 292 outsideRecvFlush = true, 293 saveLevel = true, 294 lgMaxSize = 4 295 ), 296 pftlbParameters: TLBParameters = TLBParameters( 297 name = "pftlb", 298 NWays = 48, 299 outReplace = false, 300 partialStaticPMP = true, 301 outsideRecvFlush = true, 302 saveLevel = true, 303 lgMaxSize = 4 304 ), 305 l2ToL1tlbParameters: TLBParameters = TLBParameters( 306 name = "l2tlb", 307 NWays = 48, 308 outReplace = false, 309 partialStaticPMP = true, 310 outsideRecvFlush = true, 311 saveLevel = true 312 ), 313 refillBothTlb: Boolean = false, 314 btlbParameters: TLBParameters = TLBParameters( 315 name = "btlb", 316 NWays = 48, 317 ), 318 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 319 NumPerfCounters: Int = 16, 320 icacheParameters: ICacheParameters = ICacheParameters( 321 tagECC = Some("parity"), 322 dataECC = Some("parity"), 323 replacer = Some("setplru"), 324 ), 325 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 326 tagECC = Some("secded"), 327 dataECC = Some("secded"), 328 replacer = Some("setplru"), 329 nMissEntries = 16, 330 nProbeEntries = 8, 331 nReleaseEntries = 18, 332 nMaxPrefetchEntry = 6, 333 )), 334 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 335 name = "l2", 336 ways = 8, 337 sets = 1024, // default 512KB L2 338 prefetch = Seq(coupledL2.prefetch.PrefetchReceiverParams(), coupledL2.prefetch.BOPParameters(), 339 coupledL2.prefetch.TPParameters()), 340 )), 341 L2NBanks: Int = 1, 342 usePTWRepeater: Boolean = false, 343 softTLB: Boolean = false, // dpi-c l1tlb debug only 344 softPTW: Boolean = false, // dpi-c l2tlb debug only 345 softPTWDelay: Int = 1 346){ 347 def vlWidth = log2Up(VLEN) + 1 348 349 /** 350 * the minimum element length of vector elements 351 */ 352 val minVecElen: Int = 8 353 354 /** 355 * the maximum number of elements in vector register 356 */ 357 val maxElemPerVreg: Int = VLEN / minVecElen 358 359 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 360 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 361 362 val intSchdParams = { 363 implicit val schdType: SchedulerType = IntScheduler() 364 SchdBlockParams(Seq( 365 IssueBlockParams(Seq( 366 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 367 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 0, 1)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(1, 1))), true, 2), 368 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 369 IssueBlockParams(Seq( 370 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 371 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 1, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(3, 1))), true, 2), 372 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 373 IssueBlockParams(Seq( 374 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 375 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, I2vCfg), Seq(IntWB(port = 4, 0), VfWB(2, 0), V0WB(port = 2, 0), VlWB(port = 0, 0), FpWB(port = 4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(5, 1)))), 376 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 377 IssueBlockParams(Seq( 378 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 379 ExeUnitParams("BJU3", Seq(CsrCfg, FenceCfg, DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(7, 1)))), 380 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 381 ), 382 numPregs = intPreg.numEntries, 383 numDeqOutside = 0, 384 schdType = schdType, 385 rfDataWidth = intPreg.dataCfg.dataWidth, 386 numUopIn = dpParams.IntDqDeqWidth, 387 ) 388 } 389 390 val fpSchdParams = { 391 implicit val schdType: SchedulerType = FpScheduler() 392 SchdBlockParams(Seq( 393 IssueBlockParams(Seq( 394 ExeUnitParams("FEX0", Seq(FaluCfg, FcvtCfg, F2vCfg, FmacCfg), Seq(FpWB(port = 0, 0), IntWB(port = 0, 2), VfWB(port = 3, 0), V0WB(port = 3, 0)), Seq(Seq(FpRD(0, 0)), Seq(FpRD(1, 0)), Seq(FpRD(2, 0)))), 395 ), numEntries = 18, numEnq = 2, numComp = 16), 396 IssueBlockParams(Seq( 397 ExeUnitParams("FEX1", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 1, 0), IntWB(port = 1, 2)), Seq(Seq(FpRD(3, 0)), Seq(FpRD(4, 0)), Seq(FpRD(5, 0)))), 398 ), numEntries = 18, numEnq = 2, numComp = 16), 399 IssueBlockParams(Seq( 400 ExeUnitParams("FEX2", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 2, 0), IntWB(port = 2, 2)), Seq(Seq(FpRD(6, 0)), Seq(FpRD(7, 0)), Seq(FpRD(8, 0)))), 401 ), numEntries = 18, numEnq = 2, numComp = 16), 402 IssueBlockParams(Seq( 403 ExeUnitParams("FEX3", Seq(FaluCfg, FmacCfg), Seq(FpWB(port = 3, 0), IntWB(port = 3, 2)), Seq(Seq(FpRD(9, 0)), Seq(FpRD(10, 0)), Seq(FpRD(11, 0)))), 404 ), numEntries = 18, numEnq = 2, numComp = 16), 405 IssueBlockParams(Seq( 406 ExeUnitParams("FEX4", Seq(FdivCfg), Seq(FpWB(port = 4, 1)), Seq(Seq(FpRD(2, 1)), Seq(FpRD(5, 1)))), 407 ExeUnitParams("FEX5", Seq(FdivCfg), Seq(FpWB(port = 3, 1)), Seq(Seq(FpRD(8, 1)), Seq(FpRD(11, 1)))), 408 ), numEntries = 18, numEnq = 2, numComp = 16), 409 ), 410 numPregs = fpPreg.numEntries, 411 numDeqOutside = 0, 412 schdType = schdType, 413 rfDataWidth = fpPreg.dataCfg.dataWidth, 414 numUopIn = dpParams.VecDqDeqWidth, 415 ) 416 } 417 418 val vfSchdParams = { 419 implicit val schdType: SchedulerType = VfScheduler() 420 SchdBlockParams(Seq( 421 IssueBlockParams(Seq( 422 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 0, 0), V0WB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(V0RD(0, 0)), Seq(VlRD(0, 0)))), 423 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 0, 1), V0WB(port = 0, 1), VlWB(port = 1, 0), IntWB(port = 1, 1), FpWB(port = 0, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(V0RD(0, 1)), Seq(VlRD(0, 1)))), 424 ), numEntries = 16, numEnq = 2, numComp = 14), 425 IssueBlockParams(Seq( 426 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg), Seq(VfWB(port = 1, 0), V0WB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(V0RD(1, 0)), Seq(VlRD(1, 0)))), 427 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 2, 1), V0WB(port = 2, 1), FpWB(port = 1, 1)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(5, 1)), Seq(V0RD(1, 1)), Seq(VlRD(1, 1)))), 428 ), numEntries = 16, numEnq = 2, numComp = 14), 429 IssueBlockParams(Seq( 430 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 3, 1), V0WB(port = 3, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(5, 2)), Seq(V0RD(1, 2)), Seq(VlRD(1, 2)))), 431 ), numEntries = 10, numEnq = 2, numComp = 8), 432 ), 433 numPregs = vfPreg.numEntries, 434 numDeqOutside = 0, 435 schdType = schdType, 436 rfDataWidth = vfPreg.dataCfg.dataWidth, 437 numUopIn = dpParams.VecDqDeqWidth, 438 ) 439 } 440 441 val memSchdParams = { 442 implicit val schdType: SchedulerType = MemScheduler() 443 val rfDataWidth = 64 444 445 SchdBlockParams(Seq( 446 IssueBlockParams(Seq( 447 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(11, 1)))), 448 ), numEntries = 16, numEnq = 2, numComp = 14), 449 IssueBlockParams(Seq( 450 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 451 ), numEntries = 16, numEnq = 2, numComp = 14), 452 IssueBlockParams(Seq( 453 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), FpWB(5, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 454 ), numEntries = 16, numEnq = 2, numComp = 14), 455 IssueBlockParams(Seq( 456 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), FpWB(6, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 457 ), numEntries = 16, numEnq = 2, numComp = 14), 458 IssueBlockParams(Seq( 459 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), FpWB(7, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 460 ), numEntries = 16, numEnq = 2, numComp = 14), 461 IssueBlockParams(Seq( 462 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg), Seq(VfWB(4, 0), V0WB(4, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(V0RD(2, 0)), Seq(VlRD(2, 0)))), 463 ), numEntries = 16, numEnq = 2, numComp = 14), 464 IssueBlockParams(Seq( 465 ExeUnitParams("VLSU1", Seq(VlduCfg, VstuCfg), Seq(VfWB(5, 0), V0WB(5, 0)), Seq(Seq(VfRD(9, 0)), Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(V0RD(3, 0)), Seq(VlRD(3, 0)))), 466 ), numEntries = 16, numEnq = 2, numComp = 14), 467 IssueBlockParams(Seq( 468 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), FpRD(12, 0)))), 469 ), numEntries = 16, numEnq = 2, numComp = 14), 470 IssueBlockParams(Seq( 471 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), FpRD(13, 0)))), 472 ), numEntries = 16, numEnq = 2, numComp = 14), 473 ), 474 numPregs = intPreg.numEntries max vfPreg.numEntries, 475 numDeqOutside = 0, 476 schdType = schdType, 477 rfDataWidth = rfDataWidth, 478 numUopIn = dpParams.LsDqDeqWidth, 479 ) 480 } 481 482 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 483 484 def iqWakeUpParams = { 485 Seq( 486 WakeUpConfig( 487 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 488 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 489 ), 490 // TODO: add load -> fp slow wakeup 491 WakeUpConfig( 492 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 493 Seq("FEX0", "FEX1", "FEX2", "FEX3", "FEX4", "FEX5") 494 ), 495 WakeUpConfig( 496 Seq("FEX0", "FEX1", "FEX2", "FEX3") -> 497 Seq("STD0", "STD1") 498 ), 499// WakeUpConfig( 500// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 501// Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") 502// ), 503 ).flatten 504 } 505 506 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 507 508 val backendParams: BackendParams = backend.BackendParams( 509 Map( 510 IntScheduler() -> intSchdParams, 511 FpScheduler() -> fpSchdParams, 512 VfScheduler() -> vfSchdParams, 513 MemScheduler() -> memSchdParams, 514 ), 515 Seq( 516 intPreg, 517 fpPreg, 518 vfPreg, 519 v0Preg, 520 vlPreg, 521 fakeIntPreg 522 ), 523 iqWakeUpParams, 524 ) 525} 526 527case object DebugOptionsKey extends Field[DebugOptions] 528 529case class DebugOptions 530( 531 FPGAPlatform: Boolean = false, 532 ResetGen: Boolean = false, 533 EnableDifftest: Boolean = false, 534 AlwaysBasicDiff: Boolean = true, 535 EnableDebug: Boolean = false, 536 EnablePerfDebug: Boolean = true, 537 UseDRAMSim: Boolean = false, 538 EnableConstantin: Boolean = false, 539 EnableChiselDB: Boolean = false, 540 AlwaysBasicDB: Boolean = true, 541 EnableRollingDB: Boolean = false 542) 543 544trait HasXSParameter { 545 546 implicit val p: Parameters 547 548 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 549 final val PageOffsetWidth = 12 550 def NodeIDWidth = p(SoCParamsKey).NodeIDWidth // NodeID width among NoC 551 552 def coreParams = p(XSCoreParamsKey) 553 def env = p(DebugOptionsKey) 554 555 def XLEN = coreParams.XLEN 556 def VLEN = coreParams.VLEN 557 def ELEN = coreParams.ELEN 558 def HSXLEN = coreParams.HSXLEN 559 val minFLen = 32 560 val fLen = 64 561 def hartIdLen = p(MaxHartIdBits) 562 val xLen = XLEN 563 564 def HasMExtension = coreParams.HasMExtension 565 def HasCExtension = coreParams.HasCExtension 566 def HasHExtension = coreParams.HasHExtension 567 def HasDiv = coreParams.HasDiv 568 def HasIcache = coreParams.HasICache 569 def HasDcache = coreParams.HasDCache 570 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 571 def GPAddrBits = coreParams.GPAddrBits 572 def VAddrBits = { 573 if(HasHExtension){ 574 coreParams.GPAddrBits 575 }else{ 576 coreParams.VAddrBits 577 } 578 } // VAddrBits is Virtual Memory addr bits 579 580 def VAddrMaxBits = coreParams.VAddrBits max coreParams.GPAddrBits 581 582 def AsidLength = coreParams.AsidLength 583 def VmidLength = coreParams.VmidLength 584 def ReSelectLen = coreParams.ReSelectLen 585 def AddrBytes = AddrBits / 8 // unused 586 def DataBits = XLEN 587 def DataBytes = DataBits / 8 588 def VDataBytes = VLEN / 8 589 def HasFPU = coreParams.HasFPU 590 def HasVPU = coreParams.HasVPU 591 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 592 def FetchWidth = coreParams.FetchWidth 593 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 594 def EnableBPU = coreParams.EnableBPU 595 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 596 def EnableRAS = coreParams.EnableRAS 597 def EnableLB = coreParams.EnableLB 598 def EnableLoop = coreParams.EnableLoop 599 def EnableSC = coreParams.EnableSC 600 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 601 def HistoryLength = coreParams.HistoryLength 602 def EnableGHistDiff = coreParams.EnableGHistDiff 603 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 604 def EnableClockGate = coreParams.EnableClockGate 605 def UbtbGHRLength = coreParams.UbtbGHRLength 606 def UbtbSize = coreParams.UbtbSize 607 def EnableFauFTB = coreParams.EnableFauFTB 608 def FtbSize = coreParams.FtbSize 609 def FtbWays = coreParams.FtbWays 610 def RasSize = coreParams.RasSize 611 def RasSpecSize = coreParams.RasSpecSize 612 def RasCtrSize = coreParams.RasCtrSize 613 614 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 615 coreParams.branchPredictor(resp_in, p) 616 } 617 def numBr = coreParams.numBr 618 def TageTableInfos = coreParams.TageTableInfos 619 def TageBanks = coreParams.numBr 620 def SCNRows = coreParams.SCNRows 621 def SCCtrBits = coreParams.SCCtrBits 622 def SCHistLens = coreParams.SCHistLens 623 def SCNTables = coreParams.SCNTables 624 625 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 626 case ((n, cb), h) => (n, cb, h) 627 } 628 def ITTageTableInfos = coreParams.ITTageTableInfos 629 type FoldedHistoryInfo = Tuple2[Int, Int] 630 def foldedGHistInfos = 631 (TageTableInfos.map{ case (nRows, h, t) => 632 if (h > 0) 633 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 634 else 635 Set[FoldedHistoryInfo]() 636 }.reduce(_++_).toSet ++ 637 SCTableInfos.map{ case (nRows, _, h) => 638 if (h > 0) 639 Set((h, min(log2Ceil(nRows/TageBanks), h))) 640 else 641 Set[FoldedHistoryInfo]() 642 }.reduce(_++_).toSet ++ 643 ITTageTableInfos.map{ case (nRows, h, t) => 644 if (h > 0) 645 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 646 else 647 Set[FoldedHistoryInfo]() 648 }.reduce(_++_) ++ 649 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 650 ).toList 651 652 653 654 def CacheLineSize = coreParams.CacheLineSize 655 def CacheLineHalfWord = CacheLineSize / 16 656 def ExtHistoryLength = HistoryLength + 64 657 def ICacheForceMetaECCError = coreParams.ICacheForceMetaECCError 658 def ICacheForceDataECCError = coreParams.ICacheForceDataECCError 659 def IBufSize = coreParams.IBufSize 660 def IBufNBank = coreParams.IBufNBank 661 def backendParams: BackendParams = coreParams.backendParams 662 def DecodeWidth = coreParams.DecodeWidth 663 def RenameWidth = coreParams.RenameWidth 664 def CommitWidth = coreParams.CommitWidth 665 def RobCommitWidth = coreParams.RobCommitWidth 666 def RabCommitWidth = coreParams.RabCommitWidth 667 def MaxUopSize = coreParams.MaxUopSize 668 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 669 def RenameSnapshotNum = coreParams.RenameSnapshotNum 670 def FtqSize = coreParams.FtqSize 671 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 672 def IntLogicRegs = coreParams.IntLogicRegs 673 def FpLogicRegs = coreParams.FpLogicRegs 674 def VecLogicRegs = coreParams.VecLogicRegs 675 def V0LogicRegs = coreParams.V0LogicRegs 676 def VlLogicRegs = coreParams.VlLogicRegs 677 def MaxLogicRegs = Set(IntLogicRegs, FpLogicRegs, VecLogicRegs, V0LogicRegs, VlLogicRegs).max 678 def LogicRegsWidth = log2Ceil(MaxLogicRegs) 679 def V0_IDX = coreParams.V0_IDX 680 def Vl_IDX = coreParams.Vl_IDX 681 def IntPhyRegs = coreParams.intPreg.numEntries 682 def FpPhyRegs = coreParams.fpPreg.numEntries 683 def VfPhyRegs = coreParams.vfPreg.numEntries 684 def V0PhyRegs = coreParams.v0Preg.numEntries 685 def VlPhyRegs = coreParams.vlPreg.numEntries 686 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 687 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(FpPhyRegs) max log2Up(VfPhyRegs) 688 def RobSize = coreParams.RobSize 689 def RabSize = coreParams.RabSize 690 def VTypeBufferSize = coreParams.VTypeBufferSize 691 /** 692 * the minimum element length of vector elements 693 */ 694 def minVecElen: Int = coreParams.minVecElen 695 696 /** 697 * the maximum number of elements in vector register 698 */ 699 def maxElemPerVreg: Int = coreParams.maxElemPerVreg 700 701 def IntRefCounterWidth = log2Ceil(RobSize) 702 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 703 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 704 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 705 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 706 def LoadQueueRARSize = coreParams.LoadQueueRARSize 707 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 708 def RollbackGroupSize = coreParams.RollbackGroupSize 709 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 710 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 711 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 712 def StoreQueueSize = coreParams.StoreQueueSize 713 def VirtualLoadQueueMaxStoreQueueSize = VirtualLoadQueueSize max StoreQueueSize 714 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 715 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 716 def VlsQueueSize = coreParams.VlsQueueSize 717 def dpParams = coreParams.dpParams 718 719 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 720 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 721 722 def NumRedirect = backendParams.numRedirect 723 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 724 def FtqRedirectAheadNum = NumRedirect 725 def IfuRedirectNum = coreParams.IfuRedirectNum 726 def LoadPipelineWidth = coreParams.LoadPipelineWidth 727 def StorePipelineWidth = coreParams.StorePipelineWidth 728 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 729 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 730 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 731 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 732 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 733 def VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 734 def VecMemUnitStrideMaxFlowNum = coreParams.VecMemUnitStrideMaxFlowNum 735 def VecMemLSQEnqIteratorNumberSeq = coreParams.VecMemLSQEnqIteratorNumberSeq 736 def StoreBufferSize = coreParams.StoreBufferSize 737 def StoreBufferThreshold = coreParams.StoreBufferThreshold 738 def EnsbufferWidth = coreParams.EnsbufferWidth 739 def LoadDependencyWidth = coreParams.LoadDependencyWidth 740 def VlMergeBufferSize = coreParams.VlMergeBufferSize 741 def VsMergeBufferSize = coreParams.VsMergeBufferSize 742 def UopWritebackWidth = coreParams.UopWritebackWidth 743 def VLUopWritebackWidth = coreParams.VLUopWritebackWidth 744 def VSUopWritebackWidth = coreParams.VSUopWritebackWidth 745 def VSegmentBufferSize = coreParams.VSegmentBufferSize 746 def UncacheBufferSize = coreParams.UncacheBufferSize 747 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 748 def EnableFastForward = coreParams.EnableFastForward 749 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 750 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 751 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 752 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 753 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 754 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 755 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 756 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 757 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 758 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 759 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 760 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 761 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 762 def asidLen = coreParams.MMUAsidLen 763 def vmidLen = coreParams.MMUVmidLen 764 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 765 def refillBothTlb = coreParams.refillBothTlb 766 def iwpuParam = coreParams.iwpuParameters 767 def dwpuParam = coreParams.dwpuParameters 768 def itlbParams = coreParams.itlbParameters 769 def ldtlbParams = coreParams.ldtlbParameters 770 def sttlbParams = coreParams.sttlbParameters 771 def hytlbParams = coreParams.hytlbParameters 772 def pftlbParams = coreParams.pftlbParameters 773 def l2ToL1Params = coreParams.l2ToL1tlbParameters 774 def btlbParams = coreParams.btlbParameters 775 def l2tlbParams = coreParams.l2tlbParameters 776 def NumPerfCounters = coreParams.NumPerfCounters 777 778 def instBytes = if (HasCExtension) 2 else 4 779 def instOffsetBits = log2Ceil(instBytes) 780 781 def icacheParameters = coreParams.icacheParameters 782 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 783 784 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 785 // for constrained LR/SC loop 786 def LRSCCycles = 64 787 // for lr storm 788 def LRSCBackOff = 8 789 790 // cache hierarchy configurations 791 def l1BusDataWidth = 256 792 793 // load violation predict 794 def ResetTimeMax2Pow = 20 //1078576 795 def ResetTimeMin2Pow = 10 //1024 796 // wait table parameters 797 def WaitTableSize = 1024 798 def MemPredPCWidth = log2Up(WaitTableSize) 799 def LWTUse2BitCounter = true 800 // store set parameters 801 def SSITSize = WaitTableSize 802 def LFSTSize = 32 803 def SSIDWidth = log2Up(LFSTSize) 804 def LFSTWidth = 4 805 def StoreSetEnable = true // LWT will be disabled if SS is enabled 806 def LFSTEnable = true 807 808 def PCntIncrStep: Int = 6 809 def numPCntHc: Int = 25 810 def numPCntPtw: Int = 19 811 812 def numCSRPCntFrontend = 8 813 def numCSRPCntCtrl = 8 814 def numCSRPCntLsu = 8 815 def numCSRPCntHc = 5 816 def printEventCoding = true 817 818 // Parameters for Sdtrig extension 819 protected def TriggerNum = 4 820 protected def TriggerChainMaxLength = 2 821} 822