1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan 18 19import chisel3._ 20import chisel3.util._ 21import org.chipsalliance.cde.config._ 22import chisel3.util.{Valid, ValidIO} 23import freechips.rocketchip.diplomacy._ 24import freechips.rocketchip.interrupts._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, MaxHartIdBits} 26import freechips.rocketchip.tilelink._ 27import coupledL2.{L2ParamKey, EnableCHI} 28import coupledL2.tl2tl.TL2TLCoupledL2 29import coupledL2.tl2chi.{TL2CHICoupledL2, PortIO} 30import huancun.BankBitsKey 31import system.HasSoCParameter 32import top.BusPerfMonitor 33import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer, TLLogger} 34import xiangshan.cache.mmu.TlbRequestIO 35 36class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter { 37 val ecc_error = Valid(UInt(soc.PAddrBits.W)) 38} 39 40class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors { 41 val icache = new L1BusErrorUnitInfo 42 val dcache = new L1BusErrorUnitInfo 43 val l2 = new L1BusErrorUnitInfo 44 45 override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] = 46 List( 47 Some(icache.ecc_error, "I_ECC", "Icache ecc error"), 48 Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"), 49 Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error") 50 ) 51} 52 53/** 54 * L2Top contains everything between Core and XSTile-IO 55 */ 56class L2Top()(implicit p: Parameters) extends LazyModule 57 with HasXSParameter 58 with HasSoCParameter 59{ 60 def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = { 61 val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) } 62 buffers.zipWithIndex.foreach{ case (b, i) => { 63 b.suggestName(s"${n}_${i}") 64 }} 65 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) 66 (buffers, node) 67 } 68 val enableCHI = p(EnableCHI) 69 val enableL2 = coreParams.L2CacheParamsOpt.isDefined 70 // =========== Components ============ 71 val l1_xbar = TLXbar() 72 val mmio_xbar = TLXbar() 73 val mmio_port = TLIdentityNode() // to L3 74 val memory_port = if (enableCHI && enableL2) None else Some(TLIdentityNode()) 75 val beu = LazyModule(new BusErrorUnit( 76 new XSL1BusErrors(), BusErrorUnitParams(0x38010000) 77 )) 78 79 val i_mmio_port = TLTempNode() 80 val d_mmio_port = TLTempNode() 81 82 val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform) // l1D & l1I & PTW 83 val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform, stat_latency = true) 84 val xbar_l2_buffer = TLBuffer() 85 86 val enbale_tllog = !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB 87 val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", enbale_tllog) 88 val l1i_logger = TLLogger(s"L2_L1I_${coreParams.HartId}", enbale_tllog) 89 val ptw_logger = TLLogger(s"L2_PTW_${coreParams.HartId}", enbale_tllog) 90 val ptw_to_l2_buffer = LazyModule(new TLBuffer) 91 val i_mmio_buffer = LazyModule(new TLBuffer) 92 93 val clint_int_node = IntIdentityNode() 94 val debug_int_node = IntIdentityNode() 95 val plic_int_node = IntIdentityNode() 96 97 println(s"enableCHI: ${enableCHI}") 98 val tl2tl_l2cache = if (enableL2 && !enableCHI) { 99 Some(LazyModule(new TL2TLCoupledL2()(new Config((_, _, _) => { 100 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy( 101 hartId = p(XSCoreParamsKey).HartId, 102 FPGAPlatform = debugOpts.FPGAPlatform 103 ) 104 case EnableCHI => false 105 case BankBitsKey => log2Ceil(coreParams.L2NBanks) 106 case MaxHartIdBits => p(MaxHartIdBits) 107 })))) 108 } else None 109 val tl2chi_l2cache = if (enableL2 && enableCHI) { 110 Some(LazyModule(new TL2CHICoupledL2()(new Config((_, _, _) => { 111 case L2ParamKey => coreParams.L2CacheParamsOpt.get.copy( 112 hartId = p(XSCoreParamsKey).HartId, 113 FPGAPlatform = debugOpts.FPGAPlatform 114 ) 115 case EnableCHI => true 116 // case XSCoreParamsKey => p(XSCoreParamsKey) 117 case BankBitsKey => log2Ceil(coreParams.L2NBanks) 118 case MaxHartIdBits => p(MaxHartIdBits) 119 })))) 120 } else None 121 val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64)) 122 123 // =========== Connection ============ 124 // l2 to l2_binder, then to memory_port 125 l2_binder match { 126 case Some(binder) => 127 if (!enableCHI) { 128 memory_port.get := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* binder :*= tl2tl_l2cache.get.node 129 } 130 case None => 131 memory_port.get := l1_xbar 132 } 133 134 tl2chi_l2cache match { 135 case Some(l2) => 136 l2.managerNode := TLXbar() :=* l2_binder.get :*= l2.node :*= xbar_l2_buffer :*= l1_xbar 137 l2.mmioNode := mmio_port 138 case None => 139 } 140 141 142 mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port 143 mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port 144 beu.node := TLBuffer.chainNode(1) := mmio_xbar 145 mmio_port := TLBuffer() := mmio_xbar 146 147 class L2TopImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) { 148 val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors))) 149 val reset_vector = IO(new Bundle { 150 val fromTile = Input(UInt(PAddrBits.W)) 151 val toCore = Output(UInt(PAddrBits.W)) 152 }) 153 val hartId = IO(new Bundle() { 154 val fromTile = Input(UInt(64.W)) 155 val toCore = Output(UInt(64.W)) 156 }) 157 val cpu_halt = IO(new Bundle() { 158 val fromCore = Input(Bool()) 159 val toTile = Output(Bool()) 160 }) 161 val debugTopDown = IO(new Bundle() { 162 val robTrueCommit = Input(UInt(64.W)) 163 val robHeadPaddr = Flipped(Valid(UInt(36.W))) 164 val l2MissMatch = Output(Bool()) 165 }) 166 val chi = if (enableCHI) Some(IO(new PortIO)) else None 167 val nodeID = if (enableCHI) Some(IO(Input(UInt(NodeIDWidth.W)))) else None 168 val l2_tlb_req = IO(new TlbRequestIO(nRespDups = 2)) 169 170 val resetDelayN = Module(new DelayN(UInt(PAddrBits.W), 5)) 171 172 beu.module.io.errors <> beu_errors 173 resetDelayN.io.in := reset_vector.fromTile 174 reset_vector.toCore := resetDelayN.io.out 175 hartId.toCore := hartId.fromTile 176 cpu_halt.toTile := cpu_halt.fromCore 177 dontTouch(hartId) 178 dontTouch(cpu_halt) 179 180 val l2_hint = IO(ValidIO(new L2ToL1Hint())) // TODO: parameterize this 181 if (tl2tl_l2cache.isDefined) { 182 l2_hint := tl2tl_l2cache.get.module.io.l2_hint 183 // debugTopDown <> tl2tl_l2cache.get.module.io.debugTopDown 184 tl2tl_l2cache.get.module.io.debugTopDown.robHeadPaddr := DontCare 185 tl2tl_l2cache.get.module.io.hartId := hartId.fromTile 186 tl2tl_l2cache.get.module.io.debugTopDown.robHeadPaddr := debugTopDown.robHeadPaddr 187 tl2tl_l2cache.get.module.io.debugTopDown.robTrueCommit := debugTopDown.robTrueCommit 188 debugTopDown.l2MissMatch := tl2tl_l2cache.get.module.io.debugTopDown.l2MissMatch 189 190 /* l2 tlb */ 191 l2_tlb_req.req.bits := DontCare 192 l2_tlb_req.req.valid := tl2tl_l2cache.get.module.io.l2_tlb_req.req.valid 193 l2_tlb_req.resp.ready := tl2tl_l2cache.get.module.io.l2_tlb_req.resp.ready 194 l2_tlb_req.req.bits.vaddr := tl2tl_l2cache.get.module.io.l2_tlb_req.req.bits.vaddr 195 l2_tlb_req.req.bits.cmd := tl2tl_l2cache.get.module.io.l2_tlb_req.req.bits.cmd 196 l2_tlb_req.req.bits.size := tl2tl_l2cache.get.module.io.l2_tlb_req.req.bits.size 197 l2_tlb_req.req.bits.kill := tl2tl_l2cache.get.module.io.l2_tlb_req.req.bits.kill 198 l2_tlb_req.req.bits.no_translate := tl2tl_l2cache.get.module.io.l2_tlb_req.req.bits.no_translate 199 l2_tlb_req.req_kill := tl2tl_l2cache.get.module.io.l2_tlb_req.req_kill 200 tl2tl_l2cache.get.module.io.l2_tlb_req.resp.valid := l2_tlb_req.resp.valid 201 tl2tl_l2cache.get.module.io.l2_tlb_req.req.ready := l2_tlb_req.req.ready 202 tl2tl_l2cache.get.module.io.l2_tlb_req.resp.bits.paddr.head := l2_tlb_req.resp.bits.paddr.head 203 tl2tl_l2cache.get.module.io.l2_tlb_req.resp.bits.miss := l2_tlb_req.resp.bits.miss 204 tl2tl_l2cache.get.module.io.l2_tlb_req.resp.bits.excp.head <> l2_tlb_req.resp.bits.excp.head 205 206 } else if (tl2chi_l2cache.isDefined) { 207 l2_hint := tl2chi_l2cache.get.module.io.l2_hint 208 // debugTopDown <> tl2chi_l2cache.get.module.io.debugTopDown 209 tl2chi_l2cache.get.module.io.debugTopDown.robHeadPaddr := DontCare 210 tl2chi_l2cache.get.module.io.hartId := hartId.fromTile 211 tl2chi_l2cache.get.module.io.debugTopDown.robHeadPaddr := debugTopDown.robHeadPaddr 212 tl2chi_l2cache.get.module.io.debugTopDown.robTrueCommit := debugTopDown.robTrueCommit 213 tl2chi_l2cache.get.module.io.nodeID := nodeID.get 214 debugTopDown.l2MissMatch := tl2chi_l2cache.get.module.io.debugTopDown.l2MissMatch 215 216 /* l2 tlb */ 217 l2_tlb_req.req.bits := DontCare 218 l2_tlb_req.req.valid := tl2chi_l2cache.get.module.io.l2_tlb_req.req.valid 219 l2_tlb_req.resp.ready := tl2chi_l2cache.get.module.io.l2_tlb_req.resp.ready 220 l2_tlb_req.req.bits.vaddr := tl2chi_l2cache.get.module.io.l2_tlb_req.req.bits.vaddr 221 l2_tlb_req.req.bits.cmd := tl2chi_l2cache.get.module.io.l2_tlb_req.req.bits.cmd 222 l2_tlb_req.req.bits.size := tl2chi_l2cache.get.module.io.l2_tlb_req.req.bits.size 223 l2_tlb_req.req.bits.kill := tl2chi_l2cache.get.module.io.l2_tlb_req.req.bits.kill 224 l2_tlb_req.req.bits.no_translate := tl2chi_l2cache.get.module.io.l2_tlb_req.req.bits.no_translate 225 l2_tlb_req.req_kill := tl2chi_l2cache.get.module.io.l2_tlb_req.req_kill 226 tl2chi_l2cache.get.module.io.l2_tlb_req.resp.valid := l2_tlb_req.resp.valid 227 tl2chi_l2cache.get.module.io.l2_tlb_req.req.ready := l2_tlb_req.req.ready 228 tl2chi_l2cache.get.module.io.l2_tlb_req.resp.bits.paddr.head := l2_tlb_req.resp.bits.paddr.head 229 tl2chi_l2cache.get.module.io.l2_tlb_req.resp.bits.miss := l2_tlb_req.resp.bits.miss 230 tl2chi_l2cache.get.module.io.l2_tlb_req.resp.bits.excp.head <> l2_tlb_req.resp.bits.excp.head 231 } else { 232 l2_hint := 0.U.asTypeOf(l2_hint) 233 debugTopDown <> DontCare 234 235 l2_tlb_req.req.valid := false.B 236 l2_tlb_req.req.bits := DontCare 237 l2_tlb_req.req_kill := DontCare 238 l2_tlb_req.resp.ready := true.B 239 } 240 241 chi.foreach(_ <> tl2chi_l2cache.get.module.io.chi) 242 } 243 244 lazy val module = new L2TopImp(this) 245} 246