1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15} 16 17class TageMeta extends XSBundle { 18 val provider = Valid(UInt(log2Ceil(TageNTables).W)) 19 val altDiffers = Bool() 20 val providerU = UInt(2.W) 21 val providerCtr = UInt(3.W) 22 val allocate = Valid(UInt(log2Ceil(TageNTables).W)) 23} 24 25// Branch prediction result from BPU Stage1 & 3 26class BranchPrediction extends XSBundle { 27 val redirect = Bool() 28 29 // mask off all the instrs after the first redirect instr 30 val instrValid = Vec(FetchWidth, Bool()) 31 // target of the first redirect instr in a fetch package 32 val target = UInt(VAddrBits.W) 33 // val _type = UInt(2.W) 34 35 // save these info in brq! 36 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 37 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 38 // tage meta info 39 val tageMeta = Vec(FetchWidth, (new TageMeta)) 40 // ras checkpoint, only used in Stage3 41 val rasSp = UInt(log2Up(RasSize).W) 42 val rasTopCtr = UInt(8.W) 43} 44 45// Save predecode info in icache 46class Predecode extends XSBundle { 47 val mask = UInt(FetchWidth.W) 48 val fuTypes = Vec(FetchWidth, FuType()) 49 val fuOpTypes = Vec(FetchWidth, FuOpType()) 50} 51 52// Dequeue DecodeWidth insts from Ibuffer 53class CtrlFlow extends XSBundle { 54 val instr = UInt(32.W) 55 val pc = UInt(VAddrBits.W) 56 val pnpc = UInt(VAddrBits.W) 57 val exceptionVec = Vec(16, Bool()) 58 val intrVec = Vec(12, Bool()) 59 val isRVC = Bool() 60 val isBr = Bool() 61} 62 63// Decode DecodeWidth insts at Decode Stage 64class CtrlSignals extends XSBundle { 65 val src1Type, src2Type, src3Type = SrcType() 66 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 67 val ldest = UInt(5.W) 68 val fuType = FuType() 69 val fuOpType = FuOpType() 70 val rfWen = Bool() 71 val fpWen = Bool() 72 val isXSTrap = Bool() 73 val noSpecExec = Bool() // This inst can not be speculated 74 val isBlocked = Bool() // This inst requires pipeline to be blocked 75 val isRVF = Bool() 76 val imm = UInt(XLEN.W) 77} 78 79class CfCtrl extends XSBundle { 80 val cf = new CtrlFlow 81 val ctrl = new CtrlSignals 82 val brTag = new BrqPtr 83} 84 85// CfCtrl -> MicroOp at Rename Stage 86class MicroOp extends CfCtrl { 87 88 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 89 val src1State, src2State, src3State = SrcState() 90 val freelistAllocPtr = new FreeListPtr 91 val roqIdx = UInt(RoqIdxWidth.W) 92} 93 94class Redirect extends XSBundle { 95 val pc = UInt(VAddrBits.W) // wrongly predicted pc 96 val target = UInt(VAddrBits.W) 97 val brTarget = UInt(VAddrBits.W) 98 val brTag = new BrqPtr 99 val _type = UInt(2.W) 100 val isCall = Bool() 101 val taken = Bool() 102 val hist = UInt(HistoryLength.W) 103 val tageMeta = new TageMeta 104 val fetchIdx = UInt(log2Up(FetchWidth).W) 105 val rasSp = UInt(log2Up(RasSize).W) 106 val rasTopCtr = UInt(8.W) 107 val isException = Bool() 108 val roqIdx = UInt(RoqIdxWidth.W) 109 val freelistAllocPtr = new FreeListPtr 110} 111 112class RedirectInfo extends XSBundle { 113 114 val valid = Bool() // a valid commit form brq/roq 115 val misPred = Bool() // a branch miss prediction ? 116 val redirect = new Redirect 117 118 def flush():Bool = valid && (redirect.isException || misPred) 119} 120 121class Dp1ToDp2IO extends XSBundle { 122 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 123 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 124 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 125} 126 127class DebugBundle extends XSBundle{ 128 val isMMIO = Bool() 129} 130 131class ExuInput extends XSBundle { 132 val uop = new MicroOp 133 val src1, src2, src3 = UInt(XLEN.W) 134} 135 136class ExuOutput extends XSBundle { 137 val uop = new MicroOp 138 val data = UInt(XLEN.W) 139 val redirectValid = Bool() 140 val redirect = new Redirect 141 val debug = new DebugBundle 142} 143 144class ExuIO extends XSBundle { 145 val in = Flipped(DecoupledIO(new ExuInput)) 146 val redirect = Flipped(ValidIO(new Redirect)) 147 val out = DecoupledIO(new ExuOutput) 148 149 // for Lsu 150 val dmem = new SimpleBusUC 151 val scommit = Input(UInt(3.W)) 152} 153 154class RoqCommit extends XSBundle { 155 val uop = new MicroOp 156 val isWalk = Bool() 157} 158 159class FrontendToBackendIO extends XSBundle { 160 // to backend end 161 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 162 // from backend 163 val redirectInfo = Input(new RedirectInfo) 164 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 165} 166