1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15} 16 17// Branch prediction result from BPU Stage1 & 3 18class BranchPrediction extends XSBundle { 19 val redirect = Bool() 20 21 // mask off all the instrs after the first redirect instr 22 val instrValid = Vec(FetchWidth, Bool()) 23 // target of the first redirect instr in a fetch package 24 val target = UInt(VAddrBits.W) 25 // val _type = UInt(2.W) 26 27 // save these info in brq! 28 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 29 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 30 // ras checkpoint, only used in Stage3 31 val rasSp = UInt(log2Up(RasSize).W) 32 val rasTopCtr = UInt(8.W) 33} 34 35// Save predecode info in icache 36class Predecode extends XSBundle { 37 val mask = UInt(FetchWidth.W) 38 val fuTypes = Vec(FetchWidth, FuType()) 39 val fuOpTypes = Vec(FetchWidth, FuOpType()) 40} 41 42// Dequeue DecodeWidth insts from Ibuffer 43class CtrlFlow extends XSBundle { 44 val instr = UInt(32.W) 45 val pc = UInt(VAddrBits.W) 46 val pnpc = UInt(VAddrBits.W) 47 val exceptionVec = Vec(16, Bool()) 48 val intrVec = Vec(12, Bool()) 49 val isRVC = Bool() 50 val isBr = Bool() 51} 52 53// Decode DecodeWidth insts at Decode Stage 54class CtrlSignals extends XSBundle { 55 val src1Type, src2Type, src3Type = SrcType() 56 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 57 val ldest = UInt(5.W) 58 val fuType = FuType() 59 val fuOpType = FuOpType() 60 val rfWen = Bool() 61 val fpWen = Bool() 62 val isXSTrap = Bool() 63 val noSpecExec = Bool() // This inst can not be speculated 64 val isBlocked = Bool() // This inst requires pipeline to be blocked 65 val isRVF = Bool() 66 val imm = UInt(XLEN.W) 67} 68 69class CfCtrl extends XSBundle { 70 val cf = new CtrlFlow 71 val ctrl = new CtrlSignals 72 val brTag = new BrqPtr 73} 74 75// CfCtrl -> MicroOp at Rename Stage 76class MicroOp extends CfCtrl { 77 78 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 79 val src1State, src2State, src3State = SrcState() 80 val freelistAllocPtr = new FreeListPtr 81 val roqIdx = UInt(RoqIdxWidth.W) 82} 83 84class Redirect extends XSBundle { 85 val pc = UInt(VAddrBits.W) // wrongly predicted pc 86 val target = UInt(VAddrBits.W) 87 val brTarget = UInt(VAddrBits.W) 88 val brTag = new BrqPtr 89 val _type = UInt(2.W) 90 val isCall = Bool() 91 val taken = Bool() 92 val hist = UInt(HistoryLength.W) 93 val rasSp = UInt(log2Up(RasSize).W) 94 val rasTopCtr = UInt(8.W) 95 val isException = Bool() 96 val roqIdx = UInt(RoqIdxWidth.W) 97 val freelistAllocPtr = new FreeListPtr 98} 99 100class RedirectInfo extends XSBundle { 101 102 val valid = Bool() // a valid commit form brq/roq 103 val misPred = Bool() // a branch miss prediction ? 104 val redirect = new Redirect 105 106 def flush():Bool = valid && (redirect.isException || misPred) 107} 108 109class Dp1ToDp2IO extends XSBundle { 110 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 111 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 112 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 113} 114 115class DebugBundle extends XSBundle{ 116 val isMMIO = Bool() 117} 118 119class ExuInput extends XSBundle { 120 val uop = new MicroOp 121 val src1, src2, src3 = UInt(XLEN.W) 122} 123 124class ExuOutput extends XSBundle { 125 val uop = new MicroOp 126 val data = UInt(XLEN.W) 127 val redirectValid = Bool() 128 val redirect = new Redirect 129 val debug = new DebugBundle 130} 131 132class ExuIO extends XSBundle { 133 val in = Flipped(DecoupledIO(new ExuInput)) 134 val redirect = Flipped(ValidIO(new Redirect)) 135 val out = DecoupledIO(new ExuOutput) 136 137 // for Lsu 138 val dmem = new SimpleBusUC 139 val scommit = Input(UInt(3.W)) 140} 141 142class RoqCommit extends XSBundle { 143 val uop = new MicroOp 144 val isWalk = Bool() 145} 146 147class FrontendToBackendIO extends XSBundle { 148 // to backend end 149 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 150 // from backend 151 val redirectInfo = Input(new RedirectInfo) 152 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 153} 154