1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.rename.FreeListPtr 7 8// Fetch FetchWidth x 32-bit insts from Icache 9class FetchPacket extends XSBundle { 10 val instrs = Vec(FetchWidth, UInt(32.W)) 11 val mask = UInt((FetchWidth*2).W) 12 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 13} 14 15// Dequeue DecodeWidth insts from Ibuffer 16class CtrlFlow extends XSBundle { 17 val instr = UInt(32.W) 18 val pc = UInt(VAddrBits.W) 19 val exceptionVec = Vec(16, Bool()) 20 val intrVec = Vec(12, Bool()) 21 val isRVC = Bool() 22 val isBr = Bool() 23} 24 25// Decode DecodeWidth insts at Decode Stage 26class CtrlSignals extends XSBundle { 27 val src1Type, src2Type, src3Type = SrcType() 28 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 29 val ldest = UInt(5.W) 30 val fuType = FuType() 31 val fuOpType = FuOpType() 32 val rfWen = Bool() 33 val fpWen = Bool() 34 val isXSTrap = Bool() 35 val noSpecExec = Bool() // This inst can not be speculated 36 val isBlocked = Bool() // This inst requires pipeline to be blocked 37 val isRVF = Bool() 38 val imm = UInt(XLEN.W) 39} 40 41class CfCtrl extends XSBundle { 42 val cf = new CtrlFlow 43 val ctrl = new CtrlSignals 44 val brMask = UInt(BrqSize.W) 45 val brTag = UInt(BrTagWidth.W) 46} 47 48// CfCtrl -> MicroOp at Rename Stage 49class MicroOp extends CfCtrl { 50 51 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 52 val src1State, src2State, src3State = SrcState() 53 val freelistAllocPtr = new FreeListPtr 54 val roqIdx = UInt(RoqIdxWidth.W) 55} 56 57class Redirect extends XSBundle { 58 val target = UInt(VAddrBits.W) 59 val brTag = UInt(BrTagWidth.W) 60 val isException = Bool() 61 val roqIdx = UInt(RoqIdxWidth.W) 62 val freelistAllocPtr = new FreeListPtr 63} 64 65class Dp1ToDp2IO extends XSBundle { 66 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 67 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 68 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 69} 70 71class DebugBundle extends XSBundle{ 72 val isMMIO = Bool() 73} 74 75class ExuInput extends XSBundle { 76 val uop = new MicroOp 77 val src1, src2, src3 = UInt(XLEN.W) 78} 79 80class ExuOutput extends XSBundle { 81 val uop = new MicroOp 82 val data = UInt(XLEN.W) 83 val redirectValid = Bool() 84 val redirect = new Redirect 85 val debug = new DebugBundle 86} 87 88class ExuIO extends XSBundle { 89 val in = Flipped(DecoupledIO(new ExuInput)) 90 val redirect = Flipped(ValidIO(new Redirect)) 91 val out = DecoupledIO(new ExuOutput) 92 93 // for Lsu 94 val dmem = new SimpleBusUC 95 val scommit = Input(UInt(3.W)) 96} 97 98class RoqCommit extends XSBundle { 99 val uop = new MicroOp 100 val isWalk = Bool() 101} 102 103class FrontendToBackendIO extends XSBundle { 104 // to backend end 105 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 106 // from backend 107 val redirect = Flipped(ValidIO(new Redirect)) 108 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 109} 110