1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15} 16 17class BranchPrediction extends XSBundle { 18 // mask off all the instrs after the first redirect instr 19 val instrValid = Vec(FetchWidth, Bool()) 20 // target and BTBtype of the first redirect instr in a fetch package 21 val target = UInt(VAddrBits.W) 22 val _type = UInt(2.W) 23 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 24} 25 26// Save predecode info in icache 27class Predecode extends XSBundle { 28 val mask = UInt(FetchWidth.W) 29 val fuTypes = Vec(FetchWidth, FuType()) 30 val fuOpTypes = Vec(FetchWidth, FuOpType()) 31} 32 33// Dequeue DecodeWidth insts from Ibuffer 34class CtrlFlow extends XSBundle { 35 val instr = UInt(32.W) 36 val pc = UInt(VAddrBits.W) 37 val pnpc = UInt(VAddrBits.W) 38 val exceptionVec = Vec(16, Bool()) 39 val intrVec = Vec(12, Bool()) 40 val isRVC = Bool() 41 val isBr = Bool() 42} 43 44// Decode DecodeWidth insts at Decode Stage 45class CtrlSignals extends XSBundle { 46 val src1Type, src2Type, src3Type = SrcType() 47 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 48 val ldest = UInt(5.W) 49 val fuType = FuType() 50 val fuOpType = FuOpType() 51 val rfWen = Bool() 52 val fpWen = Bool() 53 val isXSTrap = Bool() 54 val noSpecExec = Bool() // This inst can not be speculated 55 val isBlocked = Bool() // This inst requires pipeline to be blocked 56 val isRVF = Bool() 57 val imm = UInt(XLEN.W) 58} 59 60class CfCtrl extends XSBundle { 61 val cf = new CtrlFlow 62 val ctrl = new CtrlSignals 63 val brTag = new BrqPtr 64} 65 66// CfCtrl -> MicroOp at Rename Stage 67class MicroOp extends CfCtrl { 68 69 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 70 val src1State, src2State, src3State = SrcState() 71 val freelistAllocPtr = new FreeListPtr 72 val roqIdx = UInt(RoqIdxWidth.W) 73} 74 75class Redirect extends XSBundle { 76 val pc = UInt(VAddrBits.W) // wrongly predicted pc 77 val target = UInt(VAddrBits.W) 78 val brTarget = UInt(VAddrBits.W) 79 val brTag = new BrqPtr 80 val _type = UInt(2.W) 81 val isCall = Bool() 82 val taken = Bool() 83 val hist = UInt(HistoryLength.W) 84 val isException = Bool() 85 val roqIdx = UInt(RoqIdxWidth.W) 86 val freelistAllocPtr = new FreeListPtr 87} 88 89class Dp1ToDp2IO extends XSBundle { 90 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 91 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 92 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 93} 94 95class DebugBundle extends XSBundle{ 96 val isMMIO = Bool() 97} 98 99class ExuInput extends XSBundle { 100 val uop = new MicroOp 101 val src1, src2, src3 = UInt(XLEN.W) 102} 103 104class ExuOutput extends XSBundle { 105 val uop = new MicroOp 106 val data = UInt(XLEN.W) 107 val redirectValid = Bool() 108 val redirect = new Redirect 109 val debug = new DebugBundle 110} 111 112class ExuIO extends XSBundle { 113 val in = Flipped(DecoupledIO(new ExuInput)) 114 val redirect = Flipped(ValidIO(new Redirect)) 115 val out = DecoupledIO(new ExuOutput) 116 117 // for Lsu 118 val dmem = new SimpleBusUC 119 val scommit = Input(UInt(3.W)) 120} 121 122class RoqCommit extends XSBundle { 123 val uop = new MicroOp 124 val isWalk = Bool() 125} 126 127class FrontendToBackendIO extends XSBundle { 128 // to backend end 129 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 130 // from backend 131 val redirect = Flipped(ValidIO(new Redirect)) 132 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 133} 134