1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8import xiangshan.frontend.PreDecodeInfo 9 10// Fetch FetchWidth x 32-bit insts from Icache 11class FetchPacket extends XSBundle { 12 val instrs = Vec(FetchWidth, UInt(32.W)) 13 val mask = UInt((FetchWidth*2).W) 14 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 15 val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W)) 16 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W)) 17 // val btbVictimWay = UInt(log2Up(BtbWays).W) 18 val predCtr = Vec(FetchWidth*2, UInt(2.W)) 19 val btbHit = Vec(FetchWidth*2, Bool()) 20 val tageMeta = Vec(FetchWidth*2, (new TageMeta)) 21 val rasSp = UInt(log2Up(RasSize).W) 22 val rasTopCtr = UInt(8.W) 23} 24 25 26class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 27 val valid = Bool() 28 val bits = gen.asInstanceOf[T] 29 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 30} 31 32object ValidUndirectioned { 33 def apply[T <: Data](gen: T) = { 34 new ValidUndirectioned[T](gen) 35 } 36} 37 38class TageMeta extends XSBundle { 39 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 40 val altDiffers = Bool() 41 val providerU = UInt(2.W) 42 val providerCtr = UInt(3.W) 43 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 44} 45 46// Branch prediction result from BPU Stage1 & 3 47class BranchPrediction extends XSBundle { 48 val redirect = Bool() 49 50 // mask off all the instrs after the first redirect instr 51 val instrValid = Vec(FetchWidth*2, Bool()) 52 // target of the first redirect instr in a fetch package 53 val target = UInt(VAddrBits.W) 54 val lateJump = Bool() 55 // save these info in brq! 56 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 57 val hist = Vec(FetchWidth*2, UInt(HistoryLength.W)) 58 // victim way when updating btb 59 // val btbVictimWay = UInt(log2Up(BtbWays).W) 60 // 2-bit saturated counter 61 val predCtr = Vec(FetchWidth*2, UInt(2.W)) 62 val btbHit = Vec(FetchWidth*2, Bool()) 63 // tage meta info 64 val tageMeta = Vec(FetchWidth*2, (new TageMeta)) 65 // ras checkpoint, only used in Stage3 66 val rasSp = UInt(log2Up(RasSize).W) 67 val rasTopCtr = UInt(8.W) 68} 69 70class BranchPrediction extends XSBundle { 71 val redirect = Bool() 72 val jmpIdx = UInt(log2Up(PredictWidth).W) 73 val target = UInt(VAddrBits.W) 74 val saveHalfRVI = Bool() 75} 76 77class BranchInfo extends XSBundle { 78 val histPtr = UInt(log2Up(ExtHistoryLength).W) 79 val tageMeta = Vec(PredictWidth, (new TageMeta)) 80 val rasSp = UInt(log2Up(RasSize).W) 81 val rasTopCtr = UInt(8.W) 82} 83 84class Predecode extends XSBundle { 85 val mask = UInt((FetchWidth*2).W) 86 val pd = Vec(FetchWidth*2, (new PreDecodeInfo)) 87} 88 89// Dequeue DecodeWidth insts from Ibuffer 90class CtrlFlow extends XSBundle { 91 val instr = UInt(32.W) 92 val pc = UInt(VAddrBits.W) 93 val fetchOffset = UInt((log2Up(FetchWidth * 4)).W) 94 val pnpc = UInt(VAddrBits.W) 95 val hist = UInt(HistoryLength.W) 96 // val btbVictimWay = UInt(log2Up(BtbWays).W) 97 val btbPredCtr = UInt(2.W) 98 val btbHit = Bool() 99 val tageMeta = new TageMeta 100 val rasSp = UInt(log2Up(RasSize).W) 101 val rasTopCtr = UInt(8.W) 102 val exceptionVec = Vec(16, Bool()) 103 val intrVec = Vec(12, Bool()) 104 val isRVC = Bool() 105 val isBr = Bool() 106 val crossPageIPFFix = Bool() 107} 108 109// Decode DecodeWidth insts at Decode Stage 110class CtrlSignals extends XSBundle { 111 val src1Type, src2Type, src3Type = SrcType() 112 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 113 val ldest = UInt(5.W) 114 val fuType = FuType() 115 val fuOpType = FuOpType() 116 val rfWen = Bool() 117 val fpWen = Bool() 118 val isXSTrap = Bool() 119 val noSpecExec = Bool() // This inst can not be speculated 120 val isBlocked = Bool() // This inst requires pipeline to be blocked 121 val isRVF = Bool() 122 val imm = UInt(XLEN.W) 123} 124 125class CfCtrl extends XSBundle { 126 val cf = new CtrlFlow 127 val ctrl = new CtrlSignals 128 val brTag = new BrqPtr 129} 130 131// CfCtrl -> MicroOp at Rename Stage 132class MicroOp extends CfCtrl { 133 134 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 135 val src1State, src2State, src3State = SrcState() 136 val roqIdx = UInt(RoqIdxWidth.W) 137} 138 139class Redirect extends XSBundle { 140 val pc = UInt(VAddrBits.W) // wrongly predicted pc 141 val target = UInt(VAddrBits.W) 142 val brTarget = UInt(VAddrBits.W) 143 val brTag = new BrqPtr 144 val btbType = UInt(2.W) 145 val isRVC = Bool() 146 //val isCall = Bool() 147 val taken = Bool() 148 val hist = UInt(HistoryLength.W) 149 val tageMeta = new TageMeta 150 val fetchIdx = UInt(log2Up(FetchWidth*2).W) 151 // val btbVictimWay = UInt(log2Up(BtbWays).W) 152 val btbPredCtr = UInt(2.W) 153 val btbHit = Bool() 154 val rasSp = UInt(log2Up(RasSize).W) 155 val rasTopCtr = UInt(8.W) 156 val isException = Bool() 157 val roqIdx = UInt(RoqIdxWidth.W) 158} 159 160class RedirectInfo extends XSBundle { 161 162 val valid = Bool() // a valid commit form brq/roq 163 val misPred = Bool() // a branch miss prediction ? 164 val redirect = new Redirect 165 166 def flush():Bool = valid && (redirect.isException || misPred) 167} 168 169class Dp1ToDp2IO extends XSBundle { 170 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 171 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 172 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 173} 174 175class DebugBundle extends XSBundle{ 176 val isMMIO = Bool() 177} 178 179class ExuInput extends XSBundle { 180 val uop = new MicroOp 181 val src1, src2, src3 = UInt(XLEN.W) 182} 183 184class ExuOutput extends XSBundle { 185 val uop = new MicroOp 186 val data = UInt(XLEN.W) 187 val redirectValid = Bool() 188 val redirect = new Redirect 189 val debug = new DebugBundle 190} 191 192class ExuIO extends XSBundle { 193 val in = Flipped(DecoupledIO(new ExuInput)) 194 val redirect = Flipped(ValidIO(new Redirect)) 195 val out = DecoupledIO(new ExuOutput) 196 // for csr 197 val exception = Flipped(ValidIO(new MicroOp)) 198 // for Lsu 199 val dmem = new SimpleBusUC 200 val scommit = Input(UInt(3.W)) 201} 202 203class RoqCommit extends XSBundle { 204 val uop = new MicroOp 205 val isWalk = Bool() 206} 207 208class FrontendToBackendIO extends XSBundle { 209 // to backend end 210 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 211 // from backend 212 val redirectInfo = Input(new RedirectInfo) 213 val inOrderBrInfo = Input(new RedirectInfo) 214} 215