1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 16 // val btbVictimWay = UInt(log2Up(BtbWays).W) 17 val predCtr = Vec(FetchWidth, UInt(2.W)) 18 val btbHitWay = Bool() 19 val tageMeta = Vec(FetchWidth, (new TageMeta)) 20 val rasSp = UInt(log2Up(RasSize).W) 21 val rasTopCtr = UInt(8.W) 22} 23 24 25class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 26 val valid = Bool() 27 val bits = gen.asInstanceOf[T] 28 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 29} 30 31object ValidUndirectioned { 32 def apply[T <: Data](gen: T) = { 33 new ValidUndirectioned[T](gen) 34 } 35} 36 37class TageMeta extends XSBundle { 38 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 39 val altDiffers = Bool() 40 val providerU = UInt(2.W) 41 val providerCtr = UInt(3.W) 42 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 43} 44 45// Branch prediction result from BPU Stage1 & 3 46class BranchPrediction extends XSBundle { 47 val redirect = Bool() 48 49 // mask off all the instrs after the first redirect instr 50 val instrValid = Vec(FetchWidth, Bool()) 51 // target of the first redirect instr in a fetch package 52 val target = UInt(VAddrBits.W) 53 54 // save these info in brq! 55 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 56 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 57 // victim way when updating btb 58 // val btbVictimWay = UInt(log2Up(BtbWays).W) 59 // 2-bit saturated counter 60 val predCtr = Vec(FetchWidth, UInt(2.W)) 61 val btbHitWay = Bool() 62 // tage meta info 63 val tageMeta = Vec(FetchWidth, (new TageMeta)) 64 // ras checkpoint, only used in Stage3 65 val rasSp = UInt(log2Up(RasSize).W) 66 val rasTopCtr = UInt(8.W) 67} 68 69// Save predecode info in icache 70class Predecode extends XSBundle { 71 val mask = UInt(FetchWidth.W) 72 val fuTypes = Vec(FetchWidth, FuType()) 73 val fuOpTypes = Vec(FetchWidth, FuOpType()) 74} 75 76// Dequeue DecodeWidth insts from Ibuffer 77class CtrlFlow extends XSBundle { 78 val instr = UInt(32.W) 79 val pc = UInt(VAddrBits.W) 80 val fetchOffset = UInt((log2Up(FetchWidth * 4)).W) 81 val pnpc = UInt(VAddrBits.W) 82 val hist = UInt(HistoryLength.W) 83 // val btbVictimWay = UInt(log2Up(BtbWays).W) 84 val btbPredCtr = UInt(2.W) 85 val btbHitWay = Bool() 86 val tageMeta = new TageMeta 87 val rasSp = UInt(log2Up(RasSize).W) 88 val rasTopCtr = UInt(8.W) 89 val exceptionVec = Vec(16, Bool()) 90 val intrVec = Vec(12, Bool()) 91 val isRVC = Bool() 92 val isBr = Bool() 93 val crossPageIPFFix = Bool() 94} 95 96// Decode DecodeWidth insts at Decode Stage 97class CtrlSignals extends XSBundle { 98 val src1Type, src2Type, src3Type = SrcType() 99 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 100 val ldest = UInt(5.W) 101 val fuType = FuType() 102 val fuOpType = FuOpType() 103 val rfWen = Bool() 104 val fpWen = Bool() 105 val isXSTrap = Bool() 106 val noSpecExec = Bool() // This inst can not be speculated 107 val isBlocked = Bool() // This inst requires pipeline to be blocked 108 val isRVF = Bool() 109 val imm = UInt(XLEN.W) 110} 111 112class CfCtrl extends XSBundle { 113 val cf = new CtrlFlow 114 val ctrl = new CtrlSignals 115 val brTag = new BrqPtr 116} 117 118// CfCtrl -> MicroOp at Rename Stage 119class MicroOp extends CfCtrl { 120 121 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 122 val src1State, src2State, src3State = SrcState() 123 val roqIdx = UInt(RoqIdxWidth.W) 124} 125 126class Redirect extends XSBundle { 127 val pc = UInt(VAddrBits.W) // wrongly predicted pc 128 val target = UInt(VAddrBits.W) 129 val brTarget = UInt(VAddrBits.W) 130 val brTag = new BrqPtr 131 val _type = UInt(2.W) 132 //val isCall = Bool() 133 val taken = Bool() 134 val hist = UInt(HistoryLength.W) 135 val tageMeta = new TageMeta 136 val fetchIdx = UInt(log2Up(FetchWidth).W) 137 // val btbVictimWay = UInt(log2Up(BtbWays).W) 138 val btbPredCtr = UInt(2.W) 139 val btbHitWay = Bool() 140 val rasSp = UInt(log2Up(RasSize).W) 141 val rasTopCtr = UInt(8.W) 142 val isException = Bool() 143 val roqIdx = UInt(RoqIdxWidth.W) 144} 145 146class RedirectInfo extends XSBundle { 147 148 val valid = Bool() // a valid commit form brq/roq 149 val misPred = Bool() // a branch miss prediction ? 150 val redirect = new Redirect 151 152 def flush():Bool = valid && (redirect.isException || misPred) 153} 154 155class Dp1ToDp2IO extends XSBundle { 156 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 157 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 158 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 159} 160 161class DebugBundle extends XSBundle{ 162 val isMMIO = Bool() 163} 164 165class ExuInput extends XSBundle { 166 val uop = new MicroOp 167 val src1, src2, src3 = UInt(XLEN.W) 168} 169 170class ExuOutput extends XSBundle { 171 val uop = new MicroOp 172 val data = UInt(XLEN.W) 173 val redirectValid = Bool() 174 val redirect = new Redirect 175 val debug = new DebugBundle 176} 177 178class ExuIO extends XSBundle { 179 val in = Flipped(DecoupledIO(new ExuInput)) 180 val redirect = Flipped(ValidIO(new Redirect)) 181 val out = DecoupledIO(new ExuOutput) 182 183 // for Lsu 184 val dmem = new SimpleBusUC 185 val scommit = Input(UInt(3.W)) 186} 187 188class RoqCommit extends XSBundle { 189 val uop = new MicroOp 190 val isWalk = Bool() 191} 192 193class FrontendToBackendIO extends XSBundle { 194 // to backend end 195 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 196 // from backend 197 val redirectInfo = Input(new RedirectInfo) 198 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 199} 200