xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 5a67e465c647301093accfbd16f09bc53e88699d) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.frontend.PreDecodeInfo
9import xiangshan.frontend.HasBPUParameter
10
11// Fetch FetchWidth x 32-bit insts from Icache
12class FetchPacket extends XSBundle {
13  val instrs = Vec(PredictWidth, UInt(32.W))
14  val mask = UInt(PredictWidth.W)
15  // val pc = UInt(VAddrBits.W)
16  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
17  val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
18  val brInfo = Vec(PredictWidth, new BranchInfo)
19  val pd = Vec(PredictWidth, new PreDecodeInfo)
20  val ipf = Bool()
21  val crossPageIPFFix = Bool()
22}
23
24class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
25  val valid = Bool()
26  val bits = gen.cloneType.asInstanceOf[T]
27  override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]
28}
29
30object ValidUndirectioned {
31  def apply[T <: Data](gen: T) = {
32    new ValidUndirectioned[T](gen)
33  }
34}
35
36class TageMeta extends XSBundle {
37  def TageNTables = 6
38  val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
39  val altDiffers = Bool()
40  val providerU = UInt(2.W)
41  val providerCtr = UInt(3.W)
42  val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
43}
44
45class BranchPrediction extends XSBundle {
46  val redirect = Bool()
47  val taken = Bool()
48  val jmpIdx = UInt(log2Up(PredictWidth).W)
49  val hasNotTakenBrs = Bool()
50  val target = UInt(VAddrBits.W)
51  val saveHalfRVI = Bool()
52}
53
54class BranchInfo extends XSBundle with HasBPUParameter {
55  val ubtbWriteWay = UInt(log2Up(UBtbWays).W)
56  val ubtbHits = Bool()
57  val btbWriteWay = UInt(log2Up(BtbWays).W)
58  val btbHitJal = Bool()
59  val bimCtr = UInt(2.W)
60  val histPtr = UInt(log2Up(ExtHistoryLength).W)
61  val tageMeta = new TageMeta
62  val rasSp = UInt(log2Up(RasSize).W)
63  val rasTopCtr = UInt(8.W)
64  val rasToqAddr = UInt(VAddrBits.W)
65  val fetchIdx = UInt(log2Up(PredictWidth).W)
66
67  val debug_ubtb_cycle = if (BPUDebug) UInt(64.W) else UInt(0.W)
68  val debug_btb_cycle  = if (BPUDebug) UInt(64.W) else UInt(0.W)
69  val debug_tage_cycle = if (BPUDebug) UInt(64.W) else UInt(0.W)
70
71  def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = {
72    this.histPtr := histPtr
73    this.tageMeta := tageMeta
74    this.rasSp := rasSp
75    this.rasTopCtr := rasTopCtr
76    this.asUInt
77  }
78  def size = 0.U.asTypeOf(this).getWidth
79  def fromUInt(x: UInt) = x.asTypeOf(this)
80}
81
82class Predecode extends XSBundle {
83  val isFetchpcEqualFirstpc = Bool()
84  val mask = UInt((FetchWidth*2).W)
85  val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
86}
87
88class BranchUpdateInfo extends XSBundle {
89  // from backend
90  val pc = UInt(VAddrBits.W)
91  val pnpc = UInt(VAddrBits.W)
92  val target = UInt(VAddrBits.W)
93  val brTarget = UInt(VAddrBits.W)
94  val taken = Bool()
95  val fetchIdx = UInt(log2Up(FetchWidth*2).W)
96  val isMisPred = Bool()
97
98  // frontend -> backend -> frontend
99  val pd = new PreDecodeInfo
100  val brInfo = new BranchInfo
101}
102
103// Dequeue DecodeWidth insts from Ibuffer
104class CtrlFlow extends XSBundle {
105  val instr = UInt(32.W)
106  val pc = UInt(VAddrBits.W)
107  val exceptionVec = Vec(16, Bool())
108  val intrVec = Vec(12, Bool())
109  val brUpdate = new BranchUpdateInfo
110  val crossPageIPFFix = Bool()
111}
112
113// Decode DecodeWidth insts at Decode Stage
114class CtrlSignals extends XSBundle {
115  val src1Type, src2Type, src3Type = SrcType()
116  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
117  val ldest = UInt(5.W)
118  val fuType = FuType()
119  val fuOpType = FuOpType()
120  val rfWen = Bool()
121  val fpWen = Bool()
122  val isXSTrap = Bool()
123  val noSpecExec = Bool()  // This inst can not be speculated
124  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
125  val isRVF = Bool()
126  val imm = UInt(XLEN.W)
127  val commitType = CommitType()
128}
129
130class CfCtrl extends XSBundle {
131  val cf = new CtrlFlow
132  val ctrl = new CtrlSignals
133  val brTag = new BrqPtr
134}
135
136trait HasRoqIdx { this: HasXSParameter =>
137  val roqIdx = UInt(RoqIdxWidth.W)
138
139  def isAfter(thatIdx: UInt): Bool = {
140    Mux(
141      this.roqIdx.head(1) === thatIdx.head(1),
142      this.roqIdx.tail(1) > thatIdx.tail(1),
143      this.roqIdx.tail(1) < thatIdx.tail(1)
144    )
145  }
146
147  def isAfter[ T<: HasRoqIdx ](that: T): Bool = {
148    isAfter(that.roqIdx)
149  }
150
151  def needFlush(redirect: Valid[Redirect]): Bool = {
152    redirect.valid && this.isAfter(redirect.bits.roqIdx)
153  }
154}
155
156// CfCtrl -> MicroOp at Rename Stage
157class MicroOp extends CfCtrl with HasRoqIdx {
158  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
159  val src1State, src2State, src3State = SrcState()
160  val lsroqIdx = UInt(LsroqIdxWidth.W)
161}
162
163class Redirect extends XSBundle with HasRoqIdx {
164  val isException = Bool()
165  val isMisPred = Bool()
166  val isReplay = Bool()
167  val pc = UInt(VAddrBits.W)
168  val target = UInt(VAddrBits.W)
169  val brTag = new BrqPtr
170}
171
172class Dp1ToDp2IO extends XSBundle {
173  val intDqToDp2 = Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp))
174  val fpDqToDp2 = Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp))
175  val lsDqToDp2 = Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp))
176}
177
178class ReplayPregReq extends XSBundle {
179  // NOTE: set isInt and isFp both to 'false' when invalid
180  val isInt = Bool()
181  val isFp = Bool()
182  val preg = UInt(PhyRegIdxWidth.W)
183}
184
185class DebugBundle extends XSBundle{
186  val isMMIO = Bool()
187}
188
189class ExuInput extends XSBundle {
190  val uop = new MicroOp
191  val src1, src2, src3 = UInt(XLEN.W)
192}
193
194class ExuOutput extends XSBundle {
195  val uop = new MicroOp
196  val data = UInt(XLEN.W)
197  val redirectValid = Bool()
198  val redirect = new Redirect
199  val brUpdate = new BranchUpdateInfo
200  val debug = new DebugBundle
201}
202
203class ExuIO extends XSBundle {
204  val in = Flipped(DecoupledIO(new ExuInput))
205  val redirect = Flipped(ValidIO(new Redirect))
206  val out = DecoupledIO(new ExuOutput)
207  // for csr
208  val exception = Flipped(ValidIO(new MicroOp))
209  // for Lsu
210  val dmem = new SimpleBusUC
211  val mcommit = Input(UInt(3.W))
212}
213
214class RoqCommit extends XSBundle {
215  val uop = new MicroOp
216  val isWalk = Bool()
217}
218
219class TlbFeedback extends XSBundle with HasRoqIdx{
220  val hit = Bool()
221}
222
223class FrontendToBackendIO extends XSBundle {
224  // to backend end
225  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
226  // from backend
227  val redirect = Flipped(ValidIO(new Redirect))
228  val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
229  val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
230}
231
232class TlbCsrBundle extends XSBundle {
233  val satp = new Bundle {
234    val mode = UInt(4.W) // TODO: may change number to parameter
235    val asid = UInt(16.W)
236    val ppn  = UInt(44.W) // just use PAddrBits - 3 - vpnnLen
237  }
238  val priv = new Bundle {
239    val mxr = Bool()
240    val sum = Bool()
241    val imode = UInt(2.W)
242    val dmode = UInt(2.W)
243  }
244
245  override def toPrintable: Printable = {
246    p"Satp mode:0x${Hexadecimal(satp.mode)} asid:0x${Hexadecimal(satp.asid)} ppn:0x${Hexadecimal(satp.ppn)} " +
247    p"Priv mxr:${priv.mxr} sum:${priv.sum} imode:${priv.imode} dmode:${priv.dmode}"
248  }
249}
250
251class SfenceBundle extends XSBundle {
252  val valid = Bool()
253  val bits = new Bundle {
254    val rs1 = Bool()
255    val rs2 = Bool()
256    val addr = UInt(VAddrBits.W)
257  }
258
259  override def toPrintable: Printable = {
260    p"valid:0x${Hexadecimal(valid)} rs1:${bits.rs1} rs2:${bits.rs2} addr:${Hexadecimal(bits.addr)}"
261  }
262}