1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5 6// Fetch FetchWidth x 32-bit insts from Icache 7class FetchPacket extends XSBundle { 8 val instrs = Vec(FetchWidth, UInt(32.W)) 9 val mask = UInt(FetchWidth.W) 10 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 11} 12 13// Dequeue DecodeWidth insts from Ibuffer 14class CtrlFlow extends XSBundle { 15 val instr = UInt(32.W) 16 val pc = UInt(VAddrBits.W) 17 val exceptionVec = Vec(16, Bool()) 18 val intrVec = Vec(12, Bool()) 19} 20 21// Decode DecodeWidth insts at Decode Stage 22class CtrlSignals extends XSBundle { 23 24} 25 26class CfCtrl extends XSBundle { 27 val cf = new CtrlFlow 28 val ctrl = new CtrlSignals 29} 30 31// CfCtrl -> MicroOp at Rename Stage 32class MicroOp extends CfCtrl { 33 34 val psrc1, psrc2, psrc3, pdst, old_pdst = UInt(PhyRegIdxWidth.W) 35 36 val brMask = UInt(BrqSize.W) 37 val brTag = UInt(BrTagWidth.W) 38 39 val roqIdx = UInt(RoqIdxWidth.W) 40} 41 42class Redirect extends XSBundle { 43 val target = UInt(VAddrBits.W) 44 val brTag = UInt(BrTagWidth.W) 45} 46 47class Dp1ToDp2IO extends XSBundle { 48 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 49 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 50 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 51} 52 53 54class ExuInput extends XSBundle { 55 val uop = new MicroOp 56 val src1, src2, src3 = UInt(XLEN.W) 57 val isRVF = Bool() 58} 59 60class ExuOutput extends XSBundle { 61 val uop = new MicroOp 62 val data = UInt(XLEN.W) 63} 64 65class ExuIO extends XSBundle { 66 val in = Flipped(DecoupledIO(new ExuInput)) 67 val out = DecoupledIO(new ExuOutput) 68} 69 70class RoqCommit extends XSBundle { 71 val uop = new MicroOp 72} 73 74class FrontendToBackendIO extends XSBundle { 75 // to backend end 76 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 77 // from backend 78 val redirect = Flipped(ValidIO(new Redirect)) 79 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 80}