1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8import xiangshan.backend.roq.RoqPtr 9import xiangshan.frontend.PreDecodeInfo 10import xiangshan.frontend.HasBPUParameter 11import xiangshan.frontend.HasTageParameter 12 13// Fetch FetchWidth x 32-bit insts from Icache 14class FetchPacket extends XSBundle { 15 val instrs = Vec(PredictWidth, UInt(32.W)) 16 val mask = UInt(PredictWidth.W) 17 // val pc = UInt(VAddrBits.W) 18 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 19 val pnpc = Vec(PredictWidth, UInt(VAddrBits.W)) 20 val brInfo = Vec(PredictWidth, new BranchInfo) 21 val pd = Vec(PredictWidth, new PreDecodeInfo) 22 val ipf = Bool() 23 val crossPageIPFFix = Bool() 24} 25 26class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 27 val valid = Bool() 28 val bits = gen.cloneType.asInstanceOf[T] 29 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 30} 31 32object ValidUndirectioned { 33 def apply[T <: Data](gen: T) = { 34 new ValidUndirectioned[T](gen) 35 } 36} 37 38class TageMeta extends XSBundle with HasTageParameter { 39 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 40 val altDiffers = Bool() 41 val providerU = UInt(2.W) 42 val providerCtr = UInt(3.W) 43 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 44} 45 46class BranchPrediction extends XSBundle { 47 val redirect = Bool() 48 val taken = Bool() 49 val jmpIdx = UInt(log2Up(PredictWidth).W) 50 val hasNotTakenBrs = Bool() 51 val target = UInt(VAddrBits.W) 52 val saveHalfRVI = Bool() 53 val takenOnBr = Bool() 54} 55 56class BranchInfo extends XSBundle with HasBPUParameter { 57 val ubtbWriteWay = UInt(log2Up(UBtbWays).W) 58 val ubtbHits = Bool() 59 val btbWriteWay = UInt(log2Up(BtbWays).W) 60 val btbHitJal = Bool() 61 val bimCtr = UInt(2.W) 62 val histPtr = UInt(log2Up(ExtHistoryLength).W) 63 val predHistPtr = UInt(log2Up(ExtHistoryLength).W) 64 val tageMeta = new TageMeta 65 val rasSp = UInt(log2Up(RasSize).W) 66 val rasTopCtr = UInt(8.W) 67 val rasToqAddr = UInt(VAddrBits.W) 68 val fetchIdx = UInt(log2Up(PredictWidth).W) 69 val specCnt = UInt(10.W) 70 val sawNotTakenBranch = Bool() 71 72 val debug_ubtb_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W) 73 val debug_btb_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W) 74 val debug_tage_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W) 75 76 def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = { 77 this.histPtr := histPtr 78 this.tageMeta := tageMeta 79 this.rasSp := rasSp 80 this.rasTopCtr := rasTopCtr 81 this.asUInt 82 } 83 def size = 0.U.asTypeOf(this).getWidth 84 def fromUInt(x: UInt) = x.asTypeOf(this) 85} 86 87class Predecode extends XSBundle { 88 val isFetchpcEqualFirstpc = Bool() 89 val mask = UInt((FetchWidth*2).W) 90 val pd = Vec(FetchWidth*2, (new PreDecodeInfo)) 91} 92 93class BranchUpdateInfo extends XSBundle { 94 // from backend 95 val pc = UInt(VAddrBits.W) 96 val pnpc = UInt(VAddrBits.W) 97 val target = UInt(VAddrBits.W) 98 val brTarget = UInt(VAddrBits.W) 99 val taken = Bool() 100 val fetchIdx = UInt(log2Up(FetchWidth*2).W) 101 val isMisPred = Bool() 102 val brTag = new BrqPtr 103 104 // frontend -> backend -> frontend 105 val pd = new PreDecodeInfo 106 val brInfo = new BranchInfo 107} 108 109// Dequeue DecodeWidth insts from Ibuffer 110class CtrlFlow extends XSBundle { 111 val instr = UInt(32.W) 112 val pc = UInt(VAddrBits.W) 113 val exceptionVec = Vec(16, Bool()) 114 val intrVec = Vec(12, Bool()) 115 val brUpdate = new BranchUpdateInfo 116 val crossPageIPFFix = Bool() 117} 118 119// Decode DecodeWidth insts at Decode Stage 120class CtrlSignals extends XSBundle { 121 val src1Type, src2Type, src3Type = SrcType() 122 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 123 val ldest = UInt(5.W) 124 val fuType = FuType() 125 val fuOpType = FuOpType() 126 val rfWen = Bool() 127 val fpWen = Bool() 128 val isXSTrap = Bool() 129 val noSpecExec = Bool() // This inst can not be speculated 130 val isBlocked = Bool() // This inst requires pipeline to be blocked 131 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 132 val isRVF = Bool() 133 val imm = UInt(XLEN.W) 134 val commitType = CommitType() 135} 136 137class CfCtrl extends XSBundle { 138 val cf = new CtrlFlow 139 val ctrl = new CtrlSignals 140 val brTag = new BrqPtr 141} 142 143class PerfDebugInfo extends XSBundle { 144 // val fetchTime = UInt(64.W) 145 val renameTime = UInt(64.W) 146 val dispatchTime = UInt(64.W) 147 val issueTime = UInt(64.W) 148 val writebackTime = UInt(64.W) 149 // val commitTime = UInt(64.W) 150} 151 152// CfCtrl -> MicroOp at Rename Stage 153class MicroOp extends CfCtrl { 154 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 155 val src1State, src2State, src3State = SrcState() 156 val roqIdx = new RoqPtr 157 val lsroqIdx = UInt(LsroqIdxWidth.W) 158 val diffTestDebugLrScValid = Bool() 159 val debugInfo = new PerfDebugInfo 160} 161 162class Redirect extends XSBundle { 163 val roqIdx = new RoqPtr 164 val isException = Bool() 165 val isMisPred = Bool() 166 val isReplay = Bool() 167 val isFlushPipe = Bool() 168 val pc = UInt(VAddrBits.W) 169 val target = UInt(VAddrBits.W) 170 val brTag = new BrqPtr 171} 172 173class Dp1ToDp2IO extends XSBundle { 174 val intDqToDp2 = Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp)) 175 val fpDqToDp2 = Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp)) 176 val lsDqToDp2 = Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp)) 177} 178 179class ReplayPregReq extends XSBundle { 180 // NOTE: set isInt and isFp both to 'false' when invalid 181 val isInt = Bool() 182 val isFp = Bool() 183 val preg = UInt(PhyRegIdxWidth.W) 184} 185 186class DebugBundle extends XSBundle{ 187 val isMMIO = Bool() 188} 189 190class ExuInput extends XSBundle { 191 val uop = new MicroOp 192 val src1, src2, src3 = UInt(XLEN.W) 193} 194 195class ExuOutput extends XSBundle { 196 val uop = new MicroOp 197 val data = UInt(XLEN.W) 198 val redirectValid = Bool() 199 val redirect = new Redirect 200 val brUpdate = new BranchUpdateInfo 201 val debug = new DebugBundle 202} 203 204class ExuIO extends XSBundle { 205 val in = Flipped(DecoupledIO(new ExuInput)) 206 val redirect = Flipped(ValidIO(new Redirect)) 207 val out = DecoupledIO(new ExuOutput) 208 // for csr 209 val exception = Flipped(ValidIO(new MicroOp)) 210 // for Lsu 211 val dmem = new SimpleBusUC 212 val mcommit = Input(UInt(3.W)) 213} 214 215class RoqCommit extends XSBundle { 216 val uop = new MicroOp 217 val isWalk = Bool() 218} 219 220class TlbFeedback extends XSBundle { 221 val roqIdx = new RoqPtr 222 val hit = Bool() 223} 224 225class FrontendToBackendIO extends XSBundle { 226 // to backend end 227 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 228 // from backend 229 val redirect = Flipped(ValidIO(new Redirect)) 230 val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 231 val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo)) 232} 233 234class TlbCsrBundle extends XSBundle { 235 val satp = new Bundle { 236 val mode = UInt(4.W) // TODO: may change number to parameter 237 val asid = UInt(16.W) 238 val ppn = UInt(44.W) // just use PAddrBits - 3 - vpnnLen 239 } 240 val priv = new Bundle { 241 val mxr = Bool() 242 val sum = Bool() 243 val imode = UInt(2.W) 244 val dmode = UInt(2.W) 245 } 246 247 override def toPrintable: Printable = { 248 p"Satp mode:0x${Hexadecimal(satp.mode)} asid:0x${Hexadecimal(satp.asid)} ppn:0x${Hexadecimal(satp.ppn)} " + 249 p"Priv mxr:${priv.mxr} sum:${priv.sum} imode:${priv.imode} dmode:${priv.dmode}" 250 } 251} 252 253class SfenceBundle extends XSBundle { 254 val valid = Bool() 255 val bits = new Bundle { 256 val rs1 = Bool() 257 val rs2 = Bool() 258 val addr = UInt(VAddrBits.W) 259 } 260 261 override def toPrintable: Printable = { 262 p"valid:0x${Hexadecimal(valid)} rs1:${bits.rs1} rs2:${bits.rs2} addr:${Hexadecimal(bits.addr)}" 263 } 264} 265