1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14} 15 16// Dequeue DecodeWidth insts from Ibuffer 17class CtrlFlow extends XSBundle { 18 val instr = UInt(32.W) 19 val pc = UInt(VAddrBits.W) 20 val exceptionVec = Vec(16, Bool()) 21 val intrVec = Vec(12, Bool()) 22 val isRVC = Bool() 23 val isBr = Bool() 24 val crossPageIPFFix = Bool() 25} 26 27// Decode DecodeWidth insts at Decode Stage 28class CtrlSignals extends XSBundle { 29 val src1Type, src2Type, src3Type = SrcType() 30 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 31 val ldest = UInt(5.W) 32 val fuType = FuType() 33 val fuOpType = FuOpType() 34 val rfWen = Bool() 35 val fpWen = Bool() 36 val isXSTrap = Bool() 37 val noSpecExec = Bool() // This inst can not be speculated 38 val isBlocked = Bool() // This inst requires pipeline to be blocked 39 val isRVF = Bool() 40 val imm = UInt(XLEN.W) 41} 42 43class CfCtrl extends XSBundle { 44 val cf = new CtrlFlow 45 val ctrl = new CtrlSignals 46 val brTag = new BrqPtr 47} 48 49// CfCtrl -> MicroOp at Rename Stage 50class MicroOp extends CfCtrl { 51 52 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 53 val src1State, src2State, src3State = SrcState() 54 val freelistAllocPtr = new FreeListPtr 55 val roqIdx = UInt(RoqIdxWidth.W) 56 val moqIdx = UInt(MoqIdxWidth.W) 57} 58 59class Redirect extends XSBundle { 60 val target = UInt(VAddrBits.W) 61 val brTag = new BrqPtr 62 val isException = Bool() 63 val roqIdx = UInt(RoqIdxWidth.W) 64 val freelistAllocPtr = new FreeListPtr 65} 66 67class RedirectInfo extends XSBundle { 68 69 val valid = Bool() // a valid commit form brq/roq 70 val misPred = Bool() // a branch miss prediction ? 71 val redirect = new Redirect 72 73 def flush():Bool = valid && (redirect.isException || misPred) 74} 75 76class Dp1ToDp2IO extends XSBundle { 77 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 78 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 79 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 80} 81 82class DebugBundle extends XSBundle{ 83 val isMMIO = Bool() 84} 85 86class ExuInput extends XSBundle { 87 val uop = new MicroOp 88 val src1, src2, src3 = UInt(XLEN.W) 89} 90 91class ExuOutput extends XSBundle { 92 val uop = new MicroOp 93 val data = UInt(XLEN.W) 94 val redirectValid = Bool() 95 val redirect = new Redirect 96 val debug = new DebugBundle 97} 98 99class ExuIO extends XSBundle { 100 val in = Flipped(DecoupledIO(new ExuInput)) 101 val redirect = Flipped(ValidIO(new Redirect)) 102 val out = DecoupledIO(new ExuOutput) 103 104 // for Lsu 105 val dmem = new SimpleBusUC 106 val scommit = Input(UInt(3.W)) 107} 108 109class RoqCommit extends XSBundle { 110 val uop = new MicroOp 111 val isWalk = Bool() 112} 113 114class FrontendToBackendIO extends XSBundle { 115 // to backend end 116 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 117 // from backend 118 val redirectInfo = Input(new RedirectInfo) 119 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 120} 121