1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 16 // val btbVictimWay = UInt(log2Up(BtbWays).W) 17 val predCtr = Vec(FetchWidth, UInt(2.W)) 18 val btbHitWay = Bool() 19 val tageMeta = Vec(FetchWidth, (new TageMeta)) 20 val rasSp = UInt(log2Up(RasSize).W) 21 val rasTopCtr = UInt(8.W) 22} 23 24 25class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 26 val valid = Bool() 27 val bits = gen.asInstanceOf[T] 28 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 29} 30 31object ValidUndirectioned { 32 def apply[T <: Data](gen: T) = { 33 new ValidUndirectioned[T](gen) 34 } 35} 36 37class TageMeta extends XSBundle { 38 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 39 val altDiffers = Bool() 40 val providerU = UInt(2.W) 41 val providerCtr = UInt(3.W) 42 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 43} 44 45// Branch prediction result from BPU Stage1 & 3 46class BranchPrediction extends XSBundle { 47 val redirect = Bool() 48 49 // mask off all the instrs after the first redirect instr 50 val instrValid = Vec(FetchWidth, Bool()) 51 // target of the first redirect instr in a fetch package 52 val target = UInt(VAddrBits.W) 53 54 // save these info in brq! 55 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 56 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 57 // victim way when updating btb 58 // val btbVictimWay = UInt(log2Up(BtbWays).W) 59 // 2-bit saturated counter 60 val predCtr = Vec(FetchWidth, UInt(2.W)) 61 val btbHitWay = Bool() 62 // tage meta info 63 val tageMeta = Vec(FetchWidth, (new TageMeta)) 64 // ras checkpoint, only used in Stage3 65 val rasSp = UInt(log2Up(RasSize).W) 66 val rasTopCtr = UInt(8.W) 67} 68 69// Save predecode info in icache 70class Predecode extends XSBundle { 71 val mask = UInt(FetchWidth.W) 72 val fuTypes = Vec(FetchWidth, FuType()) 73 val fuOpTypes = Vec(FetchWidth, FuOpType()) 74} 75 76// Dequeue DecodeWidth insts from Ibuffer 77class CtrlFlow extends XSBundle { 78 val instr = UInt(32.W) 79 val pc = UInt(VAddrBits.W) 80 val fetchOffset = UInt((log2Up(FetchWidth * 4)).W) 81 val pnpc = UInt(VAddrBits.W) 82 val hist = UInt(HistoryLength.W) 83 // val btbVictimWay = UInt(log2Up(BtbWays).W) 84 val btbPredCtr = UInt(2.W) 85 val btbHitWay = Bool() 86 val tageMeta = new TageMeta 87 val rasSp = UInt(log2Up(RasSize).W) 88 val rasTopCtr = UInt(8.W) 89 val exceptionVec = Vec(16, Bool()) 90 val intrVec = Vec(12, Bool()) 91 val isRVC = Bool() 92 val isBr = Bool() 93 val crossPageIPFFix = Bool() 94} 95 96// Decode DecodeWidth insts at Decode Stage 97class CtrlSignals extends XSBundle { 98 val src1Type, src2Type, src3Type = SrcType() 99 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 100 val ldest = UInt(5.W) 101 val fuType = FuType() 102 val fuOpType = FuOpType() 103 val rfWen = Bool() 104 val fpWen = Bool() 105 val isXSTrap = Bool() 106 val noSpecExec = Bool() // This inst can not be speculated 107 val isBlocked = Bool() // This inst requires pipeline to be blocked 108 val isRVF = Bool() 109 val imm = UInt(XLEN.W) 110} 111 112class CfCtrl extends XSBundle { 113 val cf = new CtrlFlow 114 val ctrl = new CtrlSignals 115 val brTag = new BrqPtr 116} 117 118// CfCtrl -> MicroOp at Rename Stage 119class MicroOp extends CfCtrl { 120 121 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 122 val src1State, src2State, src3State = SrcState() 123 val roqIdx = UInt(RoqIdxWidth.W) 124 val moqIdx = UInt(MoqIdxWidth.W) 125} 126 127class Redirect extends XSBundle { 128 val pc = UInt(VAddrBits.W) // wrongly predicted pc 129 val target = UInt(VAddrBits.W) 130 val brTarget = UInt(VAddrBits.W) 131 val brTag = new BrqPtr 132 val btbType = UInt(2.W) 133 //val isCall = Bool() 134 val taken = Bool() 135 val hist = UInt(HistoryLength.W) 136 val tageMeta = new TageMeta 137 val fetchIdx = UInt(log2Up(FetchWidth).W) 138 // val btbVictimWay = UInt(log2Up(BtbWays).W) 139 val btbPredCtr = UInt(2.W) 140 val btbHitWay = Bool() 141 val rasSp = UInt(log2Up(RasSize).W) 142 val rasTopCtr = UInt(8.W) 143 val isException = Bool() 144 val roqIdx = UInt(RoqIdxWidth.W) 145} 146 147class RedirectInfo extends XSBundle { 148 149 val valid = Bool() // a valid commit form brq/roq 150 val misPred = Bool() // a branch miss prediction ? 151 val redirect = new Redirect 152 153 def flush():Bool = valid && (redirect.isException || misPred) 154} 155 156class Dp1ToDp2IO extends XSBundle { 157 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 158 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 159 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 160} 161 162class DebugBundle extends XSBundle{ 163 val isMMIO = Bool() 164} 165 166class ExuInput extends XSBundle { 167 val uop = new MicroOp 168 val src1, src2, src3 = UInt(XLEN.W) 169} 170 171class ExuOutput extends XSBundle { 172 val uop = new MicroOp 173 val data = UInt(XLEN.W) 174 val redirectValid = Bool() 175 val redirect = new Redirect 176 val debug = new DebugBundle 177} 178 179class ExuIO extends XSBundle { 180 val in = Flipped(DecoupledIO(new ExuInput)) 181 val redirect = Flipped(ValidIO(new Redirect)) 182 val out = DecoupledIO(new ExuOutput) 183 184 // for Lsu 185 val dmem = new SimpleBusUC 186 val mcommit = Input(UInt(3.W)) 187} 188 189class RoqCommit extends XSBundle { 190 val uop = new MicroOp 191 val isWalk = Bool() 192} 193 194class FrontendToBackendIO extends XSBundle { 195 // to backend end 196 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 197 // from backend 198 val redirectInfo = Input(new RedirectInfo) 199 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 200} 201