xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 3a48285b51b9a11460bdefd33dc0cc1e7cc6ded7) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.frontend.PreDecodeInfo
9import xiangshan.frontend.HasBPUParameter
10
11// Fetch FetchWidth x 32-bit insts from Icache
12class FetchPacket extends XSBundle {
13  val instrs = Vec(PredictWidth, UInt(32.W))
14  val mask = UInt(PredictWidth.W)
15  // val pc = UInt(VAddrBits.W)
16  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
17  val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
18  val brInfo = Vec(PredictWidth, new BranchInfo)
19  val pd = Vec(PredictWidth, new PreDecodeInfo)
20}
21
22class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
23  val valid = Bool()
24  val bits = gen.cloneType.asInstanceOf[T]
25  override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]
26}
27
28object ValidUndirectioned {
29  def apply[T <: Data](gen: T) = {
30    new ValidUndirectioned[T](gen)
31  }
32}
33
34class TageMeta extends XSBundle {
35  def TageNTables = 6
36  val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
37  val altDiffers = Bool()
38  val providerU = UInt(2.W)
39  val providerCtr = UInt(3.W)
40  val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
41}
42
43class BranchPrediction extends XSBundle {
44  val redirect = Bool()
45  val taken = Bool()
46  val jmpIdx = UInt(log2Up(PredictWidth).W)
47  val hasNotTakenBrs = Bool()
48  val target = UInt(VAddrBits.W)
49  val saveHalfRVI = Bool()
50  val takenOnBr = Bool()
51}
52
53class BranchInfo extends XSBundle with HasBPUParameter {
54  val ubtbWriteWay = UInt(log2Up(UBtbWays).W)
55  val ubtbHits = Bool()
56  val btbWriteWay = UInt(log2Up(BtbWays).W)
57  val btbHitJal = Bool()
58  val bimCtr = UInt(2.W)
59  val histPtr = UInt(log2Up(ExtHistoryLength).W)
60  val tageMeta = new TageMeta
61  val rasSp = UInt(log2Up(RasSize).W)
62  val rasTopCtr = UInt(8.W)
63  val rasToqAddr = UInt(VAddrBits.W)
64  val fetchIdx = UInt(log2Up(PredictWidth).W)
65  val specCnt = UInt(10.W)
66  val sawNotTakenBranch = Bool()
67
68  val debug_ubtb_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W)
69  val debug_btb_cycle  = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W)
70  val debug_tage_cycle = if (EnableBPUTimeRecord) UInt(64.W) else UInt(0.W)
71
72  def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = {
73    this.histPtr := histPtr
74    this.tageMeta := tageMeta
75    this.rasSp := rasSp
76    this.rasTopCtr := rasTopCtr
77    this.asUInt
78  }
79  def size = 0.U.asTypeOf(this).getWidth
80  def fromUInt(x: UInt) = x.asTypeOf(this)
81}
82
83class Predecode extends XSBundle {
84  val isFetchpcEqualFirstpc = Bool()
85  val mask = UInt((FetchWidth*2).W)
86  val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
87}
88
89class BranchUpdateInfo extends XSBundle {
90  // from backend
91  val pc = UInt(VAddrBits.W)
92  val pnpc = UInt(VAddrBits.W)
93  val target = UInt(VAddrBits.W)
94  val brTarget = UInt(VAddrBits.W)
95  val taken = Bool()
96  val fetchIdx = UInt(log2Up(FetchWidth*2).W)
97  val isMisPred = Bool()
98  val brTag = new BrqPtr
99
100  // frontend -> backend -> frontend
101  val pd = new PreDecodeInfo
102  val brInfo = new BranchInfo
103}
104
105// Dequeue DecodeWidth insts from Ibuffer
106class CtrlFlow extends XSBundle {
107  val instr = UInt(32.W)
108  val pc = UInt(VAddrBits.W)
109  val exceptionVec = Vec(16, Bool())
110  val intrVec = Vec(12, Bool())
111  val brUpdate = new BranchUpdateInfo
112  val crossPageIPFFix = Bool()
113}
114
115// Decode DecodeWidth insts at Decode Stage
116class CtrlSignals extends XSBundle {
117  val src1Type, src2Type, src3Type = SrcType()
118  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
119  val ldest = UInt(5.W)
120  val fuType = FuType()
121  val fuOpType = FuOpType()
122  val rfWen = Bool()
123  val fpWen = Bool()
124  val isXSTrap = Bool()
125  val noSpecExec = Bool()  // This inst can not be speculated
126  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
127  val isRVF = Bool()
128  val imm = UInt(XLEN.W)
129  val commitType = CommitType()
130}
131
132class CfCtrl extends XSBundle {
133  val cf = new CtrlFlow
134  val ctrl = new CtrlSignals
135  val brTag = new BrqPtr
136}
137
138trait HasRoqIdx { this: HasXSParameter =>
139  val roqIdx = UInt(RoqIdxWidth.W)
140
141  def isAfter(thatIdx: UInt): Bool = {
142    Mux(
143      this.roqIdx.head(1) === thatIdx.head(1),
144      this.roqIdx.tail(1) > thatIdx.tail(1),
145      this.roqIdx.tail(1) < thatIdx.tail(1)
146    )
147  }
148
149  def isAfter[ T<: HasRoqIdx ](that: T): Bool = {
150    isAfter(that.roqIdx)
151  }
152
153  def needFlush(redirect: Valid[Redirect]): Bool = {
154    redirect.valid && this.isAfter(redirect.bits.roqIdx)
155  }
156}
157
158// CfCtrl -> MicroOp at Rename Stage
159class MicroOp extends CfCtrl with HasRoqIdx {
160  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
161  val src1State, src2State, src3State = SrcState()
162  val lsroqIdx = UInt(LsroqIdxWidth.W)
163}
164
165class Redirect extends XSBundle with HasRoqIdx {
166  val isException = Bool()
167  val isMisPred = Bool()
168  val isReplay = Bool()
169  val pc = UInt(VAddrBits.W)
170  val target = UInt(VAddrBits.W)
171  val brTag = new BrqPtr
172}
173
174class Dp1ToDp2IO extends XSBundle {
175  val intDqToDp2 = Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp))
176  val fpDqToDp2 = Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp))
177  val lsDqToDp2 = Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp))
178}
179
180class ReplayPregReq extends XSBundle {
181  // NOTE: set isInt and isFp both to 'false' when invalid
182  val isInt = Bool()
183  val isFp = Bool()
184  val preg = UInt(PhyRegIdxWidth.W)
185}
186
187class DebugBundle extends XSBundle{
188  val isMMIO = Bool()
189}
190
191class ExuInput extends XSBundle {
192  val uop = new MicroOp
193  val src1, src2, src3 = UInt(XLEN.W)
194}
195
196class ExuOutput extends XSBundle {
197  val uop = new MicroOp
198  val data = UInt(XLEN.W)
199  val redirectValid = Bool()
200  val redirect = new Redirect
201  val brUpdate = new BranchUpdateInfo
202  val debug = new DebugBundle
203}
204
205class ExuIO extends XSBundle {
206  val in = Flipped(DecoupledIO(new ExuInput))
207  val redirect = Flipped(ValidIO(new Redirect))
208  val out = DecoupledIO(new ExuOutput)
209  // for csr
210  val exception = Flipped(ValidIO(new MicroOp))
211  // for Lsu
212  val dmem = new SimpleBusUC
213  val mcommit = Input(UInt(3.W))
214}
215
216class RoqCommit extends XSBundle {
217  val uop = new MicroOp
218  val isWalk = Bool()
219}
220
221class TlbFeedback extends XSBundle with HasRoqIdx{
222  val hit = Bool()
223}
224
225class FrontendToBackendIO extends XSBundle {
226  // to backend end
227  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
228  // from backend
229  val redirect = Flipped(ValidIO(new Redirect))
230  val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
231  val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
232}
233
234class TlbCsrBundle extends XSBundle {
235  val satp = new Bundle {
236    val mode = UInt(4.W) // TODO: may change number to parameter
237    val asid = UInt(16.W)
238    val ppn  = UInt(44.W) // just use PAddrBits - 3 - vpnnLen
239  }
240  val priv = new Bundle {
241    val mxr = Bool()
242    val sum = Bool()
243    val imode = UInt(2.W)
244    val dmode = UInt(2.W)
245  }
246
247  override def toPrintable: Printable = {
248    p"Satp mode:0x${Hexadecimal(satp.mode)} asid:0x${Hexadecimal(satp.asid)} ppn:0x${Hexadecimal(satp.ppn)} " +
249    p"Priv mxr:${priv.mxr} sum:${priv.sum} imode:${priv.imode} dmode:${priv.dmode}"
250  }
251}
252
253class SfenceBundle extends XSBundle {
254  val valid = Bool()
255  val bits = new Bundle {
256    val rs1 = Bool()
257    val rs2 = Bool()
258    val addr = UInt(VAddrBits.W)
259  }
260
261  override def toPrintable: Printable = {
262    p"valid:0x${Hexadecimal(valid)} rs1:${bits.rs1} rs2:${bits.rs2} addr:${Hexadecimal(bits.addr)}"
263  }
264}