1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15} 16 17 18class ValidND[T <: Data](gen: T) extends Bundle { 19 val valid = Bool() 20 val bits = gen.asInstanceOf[T] 21 override def cloneType = new ValidND(gen).asInstanceOf[this.type] 22} 23 24object ValidND { 25 def apply[T<:Data](in: T) = { 26 new ValidND[T](in) 27 } 28} 29 30class TageMeta extends XSBundle { 31 val provider = ValidND(UInt(log2Ceil(TageNTables).W)) 32 val altDiffers = Bool() 33 val providerU = UInt(2.W) 34 val providerCtr = UInt(3.W) 35 val allocate = ValidND(UInt(log2Ceil(TageNTables).W)) 36} 37 38// Branch prediction result from BPU Stage1 & 3 39class BranchPrediction extends XSBundle { 40 val redirect = Bool() 41 42 // mask off all the instrs after the first redirect instr 43 val instrValid = Vec(FetchWidth, Bool()) 44 // target of the first redirect instr in a fetch package 45 val target = UInt(VAddrBits.W) 46 // val _type = UInt(2.W) 47 48 // save these info in brq! 49 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 50 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 51 // tage meta info 52 val tageMeta = Vec(FetchWidth, (new TageMeta)) 53 // ras checkpoint, only used in Stage3 54 val rasSp = UInt(log2Up(RasSize).W) 55 val rasTopCtr = UInt(8.W) 56} 57 58// Save predecode info in icache 59class Predecode extends XSBundle { 60 val mask = UInt(FetchWidth.W) 61 val fuTypes = Vec(FetchWidth, FuType()) 62 val fuOpTypes = Vec(FetchWidth, FuOpType()) 63} 64 65// Dequeue DecodeWidth insts from Ibuffer 66class CtrlFlow extends XSBundle { 67 val instr = UInt(32.W) 68 val pc = UInt(VAddrBits.W) 69 val pnpc = UInt(VAddrBits.W) 70 val exceptionVec = Vec(16, Bool()) 71 val intrVec = Vec(12, Bool()) 72 val isRVC = Bool() 73 val isBr = Bool() 74} 75 76// Decode DecodeWidth insts at Decode Stage 77class CtrlSignals extends XSBundle { 78 val src1Type, src2Type, src3Type = SrcType() 79 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 80 val ldest = UInt(5.W) 81 val fuType = FuType() 82 val fuOpType = FuOpType() 83 val rfWen = Bool() 84 val fpWen = Bool() 85 val isXSTrap = Bool() 86 val noSpecExec = Bool() // This inst can not be speculated 87 val isBlocked = Bool() // This inst requires pipeline to be blocked 88 val isRVF = Bool() 89 val imm = UInt(XLEN.W) 90} 91 92class CfCtrl extends XSBundle { 93 val cf = new CtrlFlow 94 val ctrl = new CtrlSignals 95 val brTag = new BrqPtr 96} 97 98// CfCtrl -> MicroOp at Rename Stage 99class MicroOp extends CfCtrl { 100 101 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 102 val src1State, src2State, src3State = SrcState() 103 val freelistAllocPtr = new FreeListPtr 104 val roqIdx = UInt(RoqIdxWidth.W) 105} 106 107class Redirect extends XSBundle { 108 val pc = UInt(VAddrBits.W) // wrongly predicted pc 109 val target = UInt(VAddrBits.W) 110 val brTarget = UInt(VAddrBits.W) 111 val brTag = new BrqPtr 112 val _type = UInt(2.W) 113 val isCall = Bool() 114 val taken = Bool() 115 val hist = UInt(HistoryLength.W) 116 val tageMeta = new TageMeta 117 val fetchIdx = UInt(log2Up(FetchWidth).W) 118 val rasSp = UInt(log2Up(RasSize).W) 119 val rasTopCtr = UInt(8.W) 120 val isException = Bool() 121 val roqIdx = UInt(RoqIdxWidth.W) 122 val freelistAllocPtr = new FreeListPtr 123} 124 125class RedirectInfo extends XSBundle { 126 127 val valid = Bool() // a valid commit form brq/roq 128 val misPred = Bool() // a branch miss prediction ? 129 val redirect = new Redirect 130 131 def flush():Bool = valid && (redirect.isException || misPred) 132} 133 134class Dp1ToDp2IO extends XSBundle { 135 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 136 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 137 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 138} 139 140class DebugBundle extends XSBundle{ 141 val isMMIO = Bool() 142} 143 144class ExuInput extends XSBundle { 145 val uop = new MicroOp 146 val src1, src2, src3 = UInt(XLEN.W) 147} 148 149class ExuOutput extends XSBundle { 150 val uop = new MicroOp 151 val data = UInt(XLEN.W) 152 val redirectValid = Bool() 153 val redirect = new Redirect 154 val debug = new DebugBundle 155} 156 157class ExuIO extends XSBundle { 158 val in = Flipped(DecoupledIO(new ExuInput)) 159 val redirect = Flipped(ValidIO(new Redirect)) 160 val out = DecoupledIO(new ExuOutput) 161 162 // for Lsu 163 val dmem = new SimpleBusUC 164 val scommit = Input(UInt(3.W)) 165} 166 167class RoqCommit extends XSBundle { 168 val uop = new MicroOp 169 val isWalk = Bool() 170} 171 172class FrontendToBackendIO extends XSBundle { 173 // to backend end 174 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 175 // from backend 176 val redirectInfo = Input(new RedirectInfo) 177 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 178} 179