xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 3449c7696d5b7112508c0a75f7f4a995c42ce632) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8
9// Fetch FetchWidth x 32-bit insts from Icache
10class FetchPacket extends XSBundle {
11  val instrs = Vec(FetchWidth, UInt(32.W))
12  val mask = UInt((FetchWidth*2).W)
13  val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
14}
15
16// Dequeue DecodeWidth insts from Ibuffer
17class CtrlFlow extends XSBundle {
18  val instr = UInt(32.W)
19  val pc = UInt(VAddrBits.W)
20  val exceptionVec = Vec(16, Bool())
21  val intrVec = Vec(12, Bool())
22  val isRVC = Bool()
23  val isBr = Bool()
24  val crossPageIPFFix = Bool()
25}
26
27// Decode DecodeWidth insts at Decode Stage
28class CtrlSignals extends XSBundle {
29  val src1Type, src2Type, src3Type = SrcType()
30  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
31  val ldest = UInt(5.W)
32  val fuType = FuType()
33  val fuOpType = FuOpType()
34  val rfWen = Bool()
35  val fpWen = Bool()
36  val isXSTrap = Bool()
37  val noSpecExec = Bool()  // This inst can not be speculated
38  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
39  val isRVF = Bool()
40  val imm = UInt(XLEN.W)
41}
42
43class CfCtrl extends XSBundle {
44  val cf = new CtrlFlow
45  val ctrl = new CtrlSignals
46  val brTag = new BrqPtr
47}
48
49// CfCtrl -> MicroOp at Rename Stage
50class MicroOp extends CfCtrl {
51
52  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
53  val src1State, src2State, src3State = SrcState()
54  val roqIdx = UInt(RoqIdxWidth.W)
55}
56
57class Redirect extends XSBundle {
58  val target = UInt(VAddrBits.W)
59  val brTag = new BrqPtr
60  val isException = Bool()
61  val roqIdx = UInt(RoqIdxWidth.W)
62}
63
64class RedirectInfo extends XSBundle {
65
66  val valid = Bool() // a valid commit form brq/roq
67  val misPred = Bool() // a branch miss prediction ?
68  val redirect = new Redirect
69
70  def flush():Bool = valid && (redirect.isException || misPred)
71}
72
73class Dp1ToDp2IO extends XSBundle {
74  val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp))
75  val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp))
76  val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp))
77}
78
79class DebugBundle extends XSBundle{
80  val isMMIO = Bool()
81}
82
83class ExuInput extends XSBundle {
84  val uop = new MicroOp
85  val src1, src2, src3 = UInt(XLEN.W)
86}
87
88class ExuOutput extends XSBundle {
89  val uop = new MicroOp
90  val data = UInt(XLEN.W)
91  val redirectValid = Bool()
92  val redirect = new Redirect
93  val debug = new DebugBundle
94}
95
96class ExuIO extends XSBundle {
97  val in = Flipped(DecoupledIO(new ExuInput))
98  val redirect = Flipped(ValidIO(new Redirect))
99  val out = DecoupledIO(new ExuOutput)
100
101  // for Lsu
102  val dmem = new SimpleBusUC
103  val scommit = Input(UInt(3.W))
104}
105
106class RoqCommit extends XSBundle {
107  val uop = new MicroOp
108  val isWalk = Bool()
109}
110
111class FrontendToBackendIO extends XSBundle {
112  // to backend end
113  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
114  // from backend
115  val redirectInfo = Input(new RedirectInfo)
116  val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred
117}
118