xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 32c22eae7556974ff8a42bf4aaff79ea5c571731) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import xiangshan.backend.brq.BrqPtr
7import xiangshan.backend.rename.FreeListPtr
8import xiangshan.frontend.PreDecodeInfo
9import xiangshan.frontend.HasBPUParameter
10
11// Fetch FetchWidth x 32-bit insts from Icache
12class FetchPacket extends XSBundle {
13  val instrs = Vec(PredictWidth, UInt(32.W))
14  val mask = UInt(PredictWidth.W)
15  // val pc = UInt(VAddrBits.W)
16  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
17  val pnpc = Vec(PredictWidth, UInt(VAddrBits.W))
18  val brInfo = Vec(PredictWidth, new BranchInfo)
19  val pd = Vec(PredictWidth, new PreDecodeInfo)
20}
21
22class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
23  val valid = Bool()
24  val bits = gen.cloneType.asInstanceOf[T]
25  override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]
26}
27
28object ValidUndirectioned {
29  def apply[T <: Data](gen: T) = {
30    new ValidUndirectioned[T](gen)
31  }
32}
33
34class TageMeta extends XSBundle {
35  def TageNTables = 6
36  val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
37  val altDiffers = Bool()
38  val providerU = UInt(2.W)
39  val providerCtr = UInt(3.W)
40  val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W))
41}
42
43class BranchPrediction extends XSBundle {
44  val redirect = Bool()
45  val taken = Bool()
46  val jmpIdx = UInt(log2Up(PredictWidth).W)
47  val hasNotTakenBrs = Bool()
48  val target = UInt(VAddrBits.W)
49  val saveHalfRVI = Bool()
50}
51
52class BranchInfo extends XSBundle with HasBPUParameter {
53  val ubtbWriteWay = UInt(log2Up(UBtbWays).W)
54  val ubtbHits = Bool()
55  val btbWriteWay = UInt(log2Up(BtbWays).W)
56  val btbHitJal = Bool()
57  val bimCtr = UInt(2.W)
58  val histPtr = UInt(log2Up(ExtHistoryLength).W)
59  val tageMeta = new TageMeta
60  val rasSp = UInt(log2Up(RasSize).W)
61  val rasTopCtr = UInt(8.W)
62  val rasToqAddr = UInt(VAddrBits.W)
63  val fetchIdx = UInt(log2Up(PredictWidth).W)
64
65  val debug_ubtb_cycle = if (BPUDebug) UInt(64.W) else UInt(0.W)
66  val debug_btb_cycle  = if (BPUDebug) UInt(64.W) else UInt(0.W)
67  val debug_tage_cycle = if (BPUDebug) UInt(64.W) else UInt(0.W)
68
69  def apply(histPtr: UInt, tageMeta: TageMeta, rasSp: UInt, rasTopCtr: UInt) = {
70    this.histPtr := histPtr
71    this.tageMeta := tageMeta
72    this.rasSp := rasSp
73    this.rasTopCtr := rasTopCtr
74    this.asUInt
75  }
76  def size = 0.U.asTypeOf(this).getWidth
77  def fromUInt(x: UInt) = x.asTypeOf(this)
78}
79
80class Predecode extends XSBundle {
81  val isFetchpcEqualFirstpc = Bool()
82  val mask = UInt((FetchWidth*2).W)
83  val pd = Vec(FetchWidth*2, (new PreDecodeInfo))
84}
85
86class BranchUpdateInfo extends XSBundle {
87  // from backend
88  val pc = UInt(VAddrBits.W)
89  val pnpc = UInt(VAddrBits.W)
90  val target = UInt(VAddrBits.W)
91  val brTarget = UInt(VAddrBits.W)
92  val taken = Bool()
93  val fetchIdx = UInt(log2Up(FetchWidth*2).W)
94  val isMisPred = Bool()
95
96  // frontend -> backend -> frontend
97  val pd = new PreDecodeInfo
98  val brInfo = new BranchInfo
99}
100
101// Dequeue DecodeWidth insts from Ibuffer
102class CtrlFlow extends XSBundle {
103  val instr = UInt(32.W)
104  val pc = UInt(VAddrBits.W)
105  val exceptionVec = Vec(16, Bool())
106  val intrVec = Vec(12, Bool())
107  val brUpdate = new BranchUpdateInfo
108  val crossPageIPFFix = Bool()
109}
110
111// Decode DecodeWidth insts at Decode Stage
112class CtrlSignals extends XSBundle {
113  val src1Type, src2Type, src3Type = SrcType()
114  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
115  val ldest = UInt(5.W)
116  val fuType = FuType()
117  val fuOpType = FuOpType()
118  val rfWen = Bool()
119  val fpWen = Bool()
120  val isXSTrap = Bool()
121  val noSpecExec = Bool()  // This inst can not be speculated
122  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
123  val isRVF = Bool()
124  val imm = UInt(XLEN.W)
125  val commitType = CommitType()
126}
127
128class CfCtrl extends XSBundle {
129  val cf = new CtrlFlow
130  val ctrl = new CtrlSignals
131  val brTag = new BrqPtr
132}
133
134trait HasRoqIdx { this: HasXSParameter =>
135  val roqIdx = UInt(RoqIdxWidth.W)
136
137  def isAfter(thatIdx: UInt): Bool = {
138    Mux(
139      this.roqIdx.head(1) === thatIdx.head(1),
140      this.roqIdx.tail(1) > thatIdx.tail(1),
141      this.roqIdx.tail(1) < thatIdx.tail(1)
142    )
143  }
144
145  def isAfter[ T<: HasRoqIdx ](that: T): Bool = {
146    isAfter(that.roqIdx)
147  }
148
149  def needFlush(redirect: Valid[Redirect]): Bool = {
150    redirect.valid && this.isAfter(redirect.bits.roqIdx)
151  }
152}
153
154// CfCtrl -> MicroOp at Rename Stage
155class MicroOp extends CfCtrl with HasRoqIdx {
156  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
157  val src1State, src2State, src3State = SrcState()
158  val lsroqIdx = UInt(LsroqIdxWidth.W)
159}
160
161class Redirect extends XSBundle with HasRoqIdx {
162  val isException = Bool()
163  val isMisPred = Bool()
164  val isReplay = Bool()
165  val pc = UInt(VAddrBits.W)
166  val target = UInt(VAddrBits.W)
167  val brTag = new BrqPtr
168}
169
170class Dp1ToDp2IO extends XSBundle {
171  val intDqToDp2 = Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp))
172  val fpDqToDp2 = Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp))
173  val lsDqToDp2 = Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp))
174}
175
176class ReplayPregReq extends XSBundle {
177  // NOTE: set isInt and isFp both to 'false' when invalid
178  val isInt = Bool()
179  val isFp = Bool()
180  val preg = UInt(PhyRegIdxWidth.W)
181}
182
183class DebugBundle extends XSBundle{
184  val isMMIO = Bool()
185}
186
187class ExuInput extends XSBundle {
188  val uop = new MicroOp
189  val src1, src2, src3 = UInt(XLEN.W)
190}
191
192class ExuOutput extends XSBundle {
193  val uop = new MicroOp
194  val data = UInt(XLEN.W)
195  val redirectValid = Bool()
196  val redirect = new Redirect
197  val brUpdate = new BranchUpdateInfo
198  val debug = new DebugBundle
199}
200
201class ExuIO extends XSBundle {
202  val in = Flipped(DecoupledIO(new ExuInput))
203  val redirect = Flipped(ValidIO(new Redirect))
204  val out = DecoupledIO(new ExuOutput)
205  // for csr
206  val exception = Flipped(ValidIO(new MicroOp))
207  // for Lsu
208  val dmem = new SimpleBusUC
209  val mcommit = Input(UInt(3.W))
210}
211
212class RoqCommit extends XSBundle {
213  val uop = new MicroOp
214  val isWalk = Bool()
215}
216
217class TlbFeedback extends XSBundle with HasRoqIdx{
218  val hit = Bool()
219}
220
221class FrontendToBackendIO extends XSBundle {
222  // to backend end
223  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
224  // from backend
225  val redirect = Flipped(ValidIO(new Redirect))
226  val outOfOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
227  val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfo))
228}
229
230class TlbCsrBundle extends XSBundle {
231  val satp = new Bundle {
232    val mode = UInt(4.W) // TODO: may change number to parameter
233    val asid = UInt(16.W)
234    val ppn  = UInt(44.W) // just use PAddrBits - 3 - vpnnLen
235  }
236  val priv = new Bundle {
237    val mxr = Bool()
238    val sum = Bool()
239    val imode = UInt(2.W)
240    val dmode = UInt(2.W)
241  }
242
243  override def toPrintable: Printable = {
244    p"Satp mode:0x${Hexadecimal(satp.mode)} asid:0x${Hexadecimal(satp.asid)} ppn:0x${Hexadecimal(satp.ppn)} " +
245    p"Priv mxr:${priv.mxr} sum:${priv.sum} imode:${priv.imode} dmode:${priv.dmode}"
246  }
247}
248
249class SfenceBundle extends XSBundle {
250  val valid = Bool()
251  val bits = new Bundle {
252    val rs1 = Bool()
253    val rs2 = Bool()
254    val addr = UInt(VAddrBits.W)
255  }
256
257  override def toPrintable: Printable = {
258    p"valid:0x${Hexadecimal(valid)} rs1:${bits.rs1} rs2:${bits.rs2} addr:${Hexadecimal(bits.addr)}"
259  }
260}