1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 15} 16 17 18class ValidUndirectioned[T <: Data](gen: T) extends Bundle { 19 val valid = Bool() 20 val bits = gen.asInstanceOf[T] 21 override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type] 22} 23 24object ValidUndirectioned { 25 def apply[T <: Data](gen: T) = { 26 new ValidUndirectioned[T](gen) 27 } 28} 29 30class TageMeta extends XSBundle { 31 val provider = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 32 val altDiffers = Bool() 33 val providerU = UInt(2.W) 34 val providerCtr = UInt(3.W) 35 val allocate = ValidUndirectioned(UInt(log2Ceil(TageNTables).W)) 36} 37 38// Branch prediction result from BPU Stage1 & 3 39class BranchPrediction extends XSBundle { 40 val redirect = Bool() 41 42 // mask off all the instrs after the first redirect instr 43 val instrValid = Vec(FetchWidth, Bool()) 44 // target of the first redirect instr in a fetch package 45 val target = UInt(VAddrBits.W) 46 47 // save these info in brq! 48 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 49 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 50 // victim way when updating btb 51 val btbVictimWay = UInt(log2Up(BtbWays).W) 52 // 2-bit saturated counter 53 val predCtr = Vec(FetchWidth, UInt(2.W)) 54 val btbHitWay = Bool() 55 // tage meta info 56 val tageMeta = Vec(FetchWidth, (new TageMeta)) 57 // ras checkpoint, only used in Stage3 58 val rasSp = UInt(log2Up(RasSize).W) 59 val rasTopCtr = UInt(8.W) 60} 61 62// Save predecode info in icache 63class Predecode extends XSBundle { 64 val mask = UInt(FetchWidth.W) 65 val fuTypes = Vec(FetchWidth, FuType()) 66 val fuOpTypes = Vec(FetchWidth, FuOpType()) 67} 68 69// Dequeue DecodeWidth insts from Ibuffer 70class CtrlFlow extends XSBundle { 71 val instr = UInt(32.W) 72 val pc = UInt(VAddrBits.W) 73 val pnpc = UInt(VAddrBits.W) 74 val exceptionVec = Vec(16, Bool()) 75 val intrVec = Vec(12, Bool()) 76 val isRVC = Bool() 77 val isBr = Bool() 78} 79 80// Decode DecodeWidth insts at Decode Stage 81class CtrlSignals extends XSBundle { 82 val src1Type, src2Type, src3Type = SrcType() 83 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 84 val ldest = UInt(5.W) 85 val fuType = FuType() 86 val fuOpType = FuOpType() 87 val rfWen = Bool() 88 val fpWen = Bool() 89 val isXSTrap = Bool() 90 val noSpecExec = Bool() // This inst can not be speculated 91 val isBlocked = Bool() // This inst requires pipeline to be blocked 92 val isRVF = Bool() 93 val imm = UInt(XLEN.W) 94} 95 96class CfCtrl extends XSBundle { 97 val cf = new CtrlFlow 98 val ctrl = new CtrlSignals 99 val brTag = new BrqPtr 100} 101 102// CfCtrl -> MicroOp at Rename Stage 103class MicroOp extends CfCtrl { 104 105 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 106 val src1State, src2State, src3State = SrcState() 107 val freelistAllocPtr = new FreeListPtr 108 val roqIdx = UInt(RoqIdxWidth.W) 109} 110 111class Redirect extends XSBundle { 112 val pc = UInt(VAddrBits.W) // wrongly predicted pc 113 val target = UInt(VAddrBits.W) 114 val brTarget = UInt(VAddrBits.W) 115 val brTag = new BrqPtr 116 val _type = UInt(2.W) 117 //val isCall = Bool() 118 val taken = Bool() 119 val hist = UInt(HistoryLength.W) 120 val tageMeta = new TageMeta 121 val fetchIdx = UInt(log2Up(FetchWidth).W) 122 val btbVictimWay = UInt(log2Up(BtbWays).W) 123 val btbPredCtr = UInt(2.W) 124 val btbHitWay = Bool() 125 val rasSp = UInt(log2Up(RasSize).W) 126 val rasTopCtr = UInt(8.W) 127 val isException = Bool() 128 val roqIdx = UInt(RoqIdxWidth.W) 129 val freelistAllocPtr = new FreeListPtr 130} 131 132class RedirectInfo extends XSBundle { 133 134 val valid = Bool() // a valid commit form brq/roq 135 val misPred = Bool() // a branch miss prediction ? 136 val redirect = new Redirect 137 138 def flush():Bool = valid && (redirect.isException || misPred) 139} 140 141class Dp1ToDp2IO extends XSBundle { 142 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 143 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 144 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 145} 146 147class DebugBundle extends XSBundle{ 148 val isMMIO = Bool() 149} 150 151class ExuInput extends XSBundle { 152 val uop = new MicroOp 153 val src1, src2, src3 = UInt(XLEN.W) 154} 155 156class ExuOutput extends XSBundle { 157 val uop = new MicroOp 158 val data = UInt(XLEN.W) 159 val redirectValid = Bool() 160 val redirect = new Redirect 161 val debug = new DebugBundle 162} 163 164class ExuIO extends XSBundle { 165 val in = Flipped(DecoupledIO(new ExuInput)) 166 val redirect = Flipped(ValidIO(new Redirect)) 167 val out = DecoupledIO(new ExuOutput) 168 169 // for Lsu 170 val dmem = new SimpleBusUC 171 val scommit = Input(UInt(3.W)) 172} 173 174class RoqCommit extends XSBundle { 175 val uop = new MicroOp 176 val isWalk = Bool() 177} 178 179class FrontendToBackendIO extends XSBundle { 180 // to backend end 181 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 182 // from backend 183 val redirectInfo = Input(new RedirectInfo) 184 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 185} 186