1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.frontend.HasTageParameter 7import xiangshan.backend.brq.BrqPtr 8import xiangshan.backend.rename.FreeListPtr 9 10// Fetch FetchWidth x 32-bit insts from Icache 11class FetchPacket extends XSBundle { 12 val instrs = Vec(FetchWidth, UInt(32.W)) 13 val mask = UInt((FetchWidth*2).W) 14 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 15 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 16} 17 18class TageMeta extends XSBundle { 19 val provider = Valid(UInt(log2Ceil(TageNTables).W)) 20 val altDiffers = Bool() 21 val providerU = UInt(2.W) 22 val providerCtr = UInt(3.W) 23 val allocate = Valid(UInt(log2Ceil(TageNTables).W)) 24} 25 26// Branch prediction result from BPU Stage1 & 3 27class BranchPrediction extends XSBundle { 28 val redirect = Bool() 29 30 // mask off all the instrs after the first redirect instr 31 val instrValid = Vec(FetchWidth, Bool()) 32 // target of the first redirect instr in a fetch package 33 val target = UInt(VAddrBits.W) 34 // val _type = UInt(2.W) 35 36 // save these info in brq! 37 // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result 38 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 39 // tage meta info 40 val tageMeta = Vec(FetchWidth, (new TageMeta)) 41 // ras checkpoint, only used in Stage3 42 val rasSp = UInt(log2Up(RasSize).W) 43 val rasTopCtr = UInt(8.W) 44} 45 46// Save predecode info in icache 47class Predecode extends XSBundle { 48 val mask = UInt(FetchWidth.W) 49 val fuTypes = Vec(FetchWidth, FuType()) 50 val fuOpTypes = Vec(FetchWidth, FuOpType()) 51} 52 53// Dequeue DecodeWidth insts from Ibuffer 54class CtrlFlow extends XSBundle { 55 val instr = UInt(32.W) 56 val pc = UInt(VAddrBits.W) 57 val pnpc = UInt(VAddrBits.W) 58 val exceptionVec = Vec(16, Bool()) 59 val intrVec = Vec(12, Bool()) 60 val isRVC = Bool() 61 val isBr = Bool() 62} 63 64// Decode DecodeWidth insts at Decode Stage 65class CtrlSignals extends XSBundle { 66 val src1Type, src2Type, src3Type = SrcType() 67 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 68 val ldest = UInt(5.W) 69 val fuType = FuType() 70 val fuOpType = FuOpType() 71 val rfWen = Bool() 72 val fpWen = Bool() 73 val isXSTrap = Bool() 74 val noSpecExec = Bool() // This inst can not be speculated 75 val isBlocked = Bool() // This inst requires pipeline to be blocked 76 val isRVF = Bool() 77 val imm = UInt(XLEN.W) 78} 79 80class CfCtrl extends XSBundle { 81 val cf = new CtrlFlow 82 val ctrl = new CtrlSignals 83 val brTag = new BrqPtr 84} 85 86// CfCtrl -> MicroOp at Rename Stage 87class MicroOp extends CfCtrl { 88 89 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 90 val src1State, src2State, src3State = SrcState() 91 val freelistAllocPtr = new FreeListPtr 92 val roqIdx = UInt(RoqIdxWidth.W) 93} 94 95class Redirect extends XSBundle { 96 val pc = UInt(VAddrBits.W) // wrongly predicted pc 97 val target = UInt(VAddrBits.W) 98 val brTarget = UInt(VAddrBits.W) 99 val brTag = new BrqPtr 100 val _type = UInt(2.W) 101 val isCall = Bool() 102 val taken = Bool() 103 val hist = UInt(HistoryLength.W) 104 val tageMeta = new TageMeta 105 val rasSp = UInt(log2Up(RasSize).W) 106 val rasTopCtr = UInt(8.W) 107 val isException = Bool() 108 val roqIdx = UInt(RoqIdxWidth.W) 109 val freelistAllocPtr = new FreeListPtr 110} 111 112class RedirectInfo extends XSBundle { 113 114 val valid = Bool() // a valid commit form brq/roq 115 val misPred = Bool() // a branch miss prediction ? 116 val redirect = new Redirect 117 118 def flush():Bool = valid && (redirect.isException || misPred) 119} 120 121class Dp1ToDp2IO extends XSBundle { 122 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 123 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 124 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 125} 126 127class DebugBundle extends XSBundle{ 128 val isMMIO = Bool() 129} 130 131class ExuInput extends XSBundle { 132 val uop = new MicroOp 133 val src1, src2, src3 = UInt(XLEN.W) 134} 135 136class ExuOutput extends XSBundle { 137 val uop = new MicroOp 138 val data = UInt(XLEN.W) 139 val redirectValid = Bool() 140 val redirect = new Redirect 141 val debug = new DebugBundle 142} 143 144class ExuIO extends XSBundle { 145 val in = Flipped(DecoupledIO(new ExuInput)) 146 val redirect = Flipped(ValidIO(new Redirect)) 147 val out = DecoupledIO(new ExuOutput) 148 149 // for Lsu 150 val dmem = new SimpleBusUC 151 val scommit = Input(UInt(3.W)) 152} 153 154class RoqCommit extends XSBundle { 155 val uop = new MicroOp 156 val isWalk = Bool() 157} 158 159class FrontendToBackendIO extends XSBundle { 160 // to backend end 161 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 162 // from backend 163 val redirectInfo = Input(new RedirectInfo) 164 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 165} 166