1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.rename.FreeListPtr 7 8// Fetch FetchWidth x 32-bit insts from Icache 9class FetchPacket extends XSBundle { 10 val instrs = Vec(FetchWidth, UInt(32.W)) 11 val mask = UInt((FetchWidth*2).W) 12 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 13 val pnpc = Vec(FetchWidth, UInt(VAddrBits.W)) 14} 15 16class BranchPrediction extends XSBundle { 17 // mask off all the instrs after the first redirect instr 18 val instrValid = Vec(FetchWidth, Bool()) 19 // target and BTBtype of the first redirect instr in a fetch package 20 val target = UInt(VAddrBits.W) 21 val _type = UInt(2.W) 22 val hist = Vec(FetchWidth, UInt(HistoryLength.W)) 23} 24 25// Save predecode info in icache 26class Predecode extends XSBundle { 27 val fuTypes = Vec(FetchWidth, FuType()) 28 val fuOpTypes = Vec(FetchWidth, FuOpType()) 29} 30 31// Dequeue DecodeWidth insts from Ibuffer 32class CtrlFlow extends XSBundle { 33 val instr = UInt(32.W) 34 val pc = UInt(VAddrBits.W) 35 val pnpc = UInt(VAddrBits.W) 36 val exceptionVec = Vec(16, Bool()) 37 val intrVec = Vec(12, Bool()) 38 val isRVC = Bool() 39 val isBr = Bool() 40} 41 42// Decode DecodeWidth insts at Decode Stage 43class CtrlSignals extends XSBundle { 44 val src1Type, src2Type, src3Type = SrcType() 45 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 46 val ldest = UInt(5.W) 47 val fuType = FuType() 48 val fuOpType = FuOpType() 49 val rfWen = Bool() 50 val fpWen = Bool() 51 val isXSTrap = Bool() 52 val noSpecExec = Bool() // This inst can not be speculated 53 val isBlocked = Bool() // This inst requires pipeline to be blocked 54 val isRVF = Bool() 55 val imm = UInt(XLEN.W) 56} 57 58class CfCtrl extends XSBundle { 59 val cf = new CtrlFlow 60 val ctrl = new CtrlSignals 61 val brMask = UInt(BrqSize.W) 62 val brTag = UInt(BrTagWidth.W) 63} 64 65// CfCtrl -> MicroOp at Rename Stage 66class MicroOp extends CfCtrl { 67 68 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 69 val src1State, src2State, src3State = SrcState() 70 val freelistAllocPtr = new FreeListPtr 71 val roqIdx = UInt(RoqIdxWidth.W) 72} 73 74class Redirect extends XSBundle { 75 val pc = UInt(VAddrBits.W) // wrongly predicted pc 76 val target = UInt(VAddrBits.W) 77 val brTarget = UInt(VAddrBits.W) 78 val brTag = UInt(BrTagWidth.W) 79 val _type = UInt(2.W) 80 val isCall = Bool() 81 val taken = Bool() 82 val hist = UInt(HistoryLength.W) 83 val isException = Bool() 84 val roqIdx = UInt(RoqIdxWidth.W) 85 val freelistAllocPtr = new FreeListPtr 86} 87 88class Dp1ToDp2IO extends XSBundle { 89 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 90 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 91 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 92} 93 94class DebugBundle extends XSBundle{ 95 val isMMIO = Bool() 96} 97 98class ExuInput extends XSBundle { 99 val uop = new MicroOp 100 val src1, src2, src3 = UInt(XLEN.W) 101} 102 103class ExuOutput extends XSBundle { 104 val uop = new MicroOp 105 val data = UInt(XLEN.W) 106 val redirectValid = Bool() 107 val redirect = new Redirect 108 val debug = new DebugBundle 109} 110 111class ExuIO extends XSBundle { 112 val in = Flipped(DecoupledIO(new ExuInput)) 113 val redirect = Flipped(ValidIO(new Redirect)) 114 val out = DecoupledIO(new ExuOutput) 115 116 // for Lsu 117 val dmem = new SimpleBusUC 118 val scommit = Input(UInt(3.W)) 119} 120 121class RoqCommit extends XSBundle { 122 val uop = new MicroOp 123 val isWalk = Bool() 124} 125 126class FrontendToBackendIO extends XSBundle { 127 // to backend end 128 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 129 // from backend 130 val redirect = Flipped(ValidIO(new Redirect)) 131 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 132} 133